[llvm] r342115 - [AMDGPU] Preliminary patch for divergence driven instruction selection. Load offset inlining pattern changed.

[Alexander Timofeev via llvm-commits]

Author: alex-t
Date: Wed Sep 12 23:34:56 2018
New Revision: 342115

URL: http://llvm.org/viewvc/llvm-project?rev=342115&view=rev
Log:
    [AMDGPU] Preliminary patch for divergence driven instruction selection. Load offset inlining pattern changed.

    Differential revision: https://reviews.llvm.org/D51975

    Reviewers: rampitec

Modified:
    llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
    llvm/trunk/test/CodeGen/AMDGPU/smrd-fold-offset.mir

Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp?rev=342115&r1=342114&r2=342115&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp Wed Sep 12 23:34:56 2018
@@ -4084,6 +4084,7 @@ void SIInstrInfo::moveToVALU(MachineInst
       // V_ADD will be removed by "Remove dead machine instructions".
       if (Add &&
           (Add->getOpcode() == AMDGPU::V_ADD_I32_e32 ||
+           Add->getOpcode() == AMDGPU::V_ADD_U32_e32 ||
            Add->getOpcode() == AMDGPU::V_ADD_U32_e64)) {
         static const unsigned SrcNames[2] = {
           AMDGPU::OpName::src0,

Modified: llvm/trunk/test/CodeGen/AMDGPU/smrd-fold-offset.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/smrd-fold-offset.mir?rev=342115&r1=342114&r2=342115&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/smrd-fold-offset.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/smrd-fold-offset.mir Wed Sep 12 23:34:56 2018
@@ -21,3 +21,26 @@ body:             |
     $vgpr0 = COPY %9
     SI_RETURN_TO_EPILOG $vgpr0
 ...
+
+# GCN: BUFFER_LOAD_DWORD_OFFEN %{{[0-9]+}}, killed %{{[0-9]+}}, 0, 4095
+---
+name:            smrd_vgpr_offset_imm_add_u32
+body:             |
+  bb.0:
+    liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0
+
+    %4:vgpr_32 = COPY $vgpr0
+    %3:sgpr_32 = COPY $sgpr3
+    %2:sgpr_32 = COPY $sgpr2
+    %1:sgpr_32 = COPY $sgpr1
+    %0:sgpr_32 = COPY $sgpr0
+    %5:sgpr_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
+    %6:sreg_32_xm0 = S_MOV_B32 4095
+    %8:vgpr_32 = COPY %6
+    %7:vgpr_32 = V_ADD_U32_e32 %4, killed %8, implicit $exec
+    %10:sreg_32 = COPY %7
+    %9:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR killed %5, killed %10, 0 :: (dereferenceable invariant load 4)
+    $vgpr0 = COPY %9
+    SI_RETURN_TO_EPILOG $vgpr0
+
+...