[llvm] r342109 - ARM: correct the relocation type for `bl` on WoA

[Saleem Abdulrasool via llvm-commits]

Author: compnerd
Date: Wed Sep 12 21:55:08 2018
New Revision: 342109

URL: http://llvm.org/viewvc/llvm-project?rev=342109&view=rev
Log:
ARM: correct the relocation type for `bl` on WoA

The `IMAGE_REL_ARM_BRANCH20T` applies only to a `b.w` instruction.  A
thumb-2 `bl` should be relocated using a `IMAGE_REL_ARM_BRANCH24T`.
Correct the relocation that we emit in such a case.

Resolves PR38620!  Based on the patch by Jordan Rhee!

Modified:
    llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMWinCOFFObjectWriter.cpp
    llvm/trunk/test/MC/ARM/coff-relocations.s

Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMWinCOFFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMWinCOFFObjectWriter.cpp?rev=342109&r1=342108&r2=342109&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMWinCOFFObjectWriter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMWinCOFFObjectWriter.cpp Wed Sep 12 21:55:08 2018
@@ -75,8 +75,8 @@ unsigned ARMWinCOFFObjectWriter::getRelo
   case ARM::fixup_t2_condbranch:
     return COFF::IMAGE_REL_ARM_BRANCH20T;
   case ARM::fixup_t2_uncondbranch:
-    return COFF::IMAGE_REL_ARM_BRANCH24T;
   case ARM::fixup_arm_thumb_bl:
+    return COFF::IMAGE_REL_ARM_BRANCH24T;
   case ARM::fixup_arm_thumb_blx:
     return COFF::IMAGE_REL_ARM_BLX23T;
   case ARM::fixup_t2_movw_lo16:

Modified: llvm/trunk/test/MC/ARM/coff-relocations.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/coff-relocations.s?rev=342109&r1=342108&r2=342109&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/coff-relocations.s (original)
+++ llvm/trunk/test/MC/ARM/coff-relocations.s Wed Sep 12 21:55:08 2018
@@ -11,13 +11,20 @@
 	.global target
 
 	.thumb_func
-branch24t:
+branch24t_0:
 	b target
 
-@ CHECK-ENCODING-LABEL: branch24t:
+@ CHECK-ENCODING-LABEL: branch24t_0:
 @ CHECK-ENCODING-NEXT: b.w #0
 
 	.thumb_func
+branch24t_1:
+	bl target
+
+@ CHECK-ENCODING-LABEL: branch24t_1:
+@ CHECK-ENCODING-NEXR: bl #0
+
+	.thumb_func
 branch20t:
 	bcc target
 
@@ -26,10 +33,10 @@ branch20t:
 
 	.thumb_func
 blx23t:
-	bl target
+	blx target
 
 @ CHECK-ENCODING-LABEL: blx23t:
-@ CHECK-ENCODING-NEXT: bl #0
+@ CHECK-ENCODING-NEXT: blx #0
 
 	.thumb_func
 mov32t:
@@ -90,12 +97,13 @@ secrel:
 @ CHECK-RELOCATION: Relocations [
 @ CHECK-RELOCATION:   Section (1) .text {
 @ CHECK-RELOCATION:     0x0 IMAGE_REL_ARM_BRANCH24T
-@ CHECK-RELOCATION:     0x4 IMAGE_REL_ARM_BRANCH20T
-@ CHECK-RELOCATION:     0x8 IMAGE_REL_ARM_BLX23T
-@ CHECK-RELOCATION:     0xC IMAGE_REL_ARM_MOV32T
-@ CHECK-RELOCATION:     0x1C IMAGE_REL_ARM_ADDR32
-@ CHECK-RELOCATION:     0x28 IMAGE_REL_ARM_ADDR32NB
-@ CHECK-RELOCATION:     0x34 IMAGE_REL_ARM_SECREL
+@ CHECK-RELOCATION:     0x4 IMAGE_REL_ARM_BRANCH24T
+@ CHECK-RELOCATION:     0x8 IMAGE_REL_ARM_BRANCH20T
+@ CHECK-RELOCATION:     0xC IMAGE_REL_ARM_BLX23T
+@ CHECK-RELOCATION:     0x10 IMAGE_REL_ARM_MOV32T
+@ CHECK-RELOCATION:     0x20 IMAGE_REL_ARM_ADDR32
+@ CHECK-RELOCATION:     0x2C IMAGE_REL_ARM_ADDR32NB
+@ CHECK-RELOCATION:     0x38 IMAGE_REL_ARM_SECREL
 @ CHECK-RELOCATION:   }
 @ CHECK-RELOCATION: ]