[llvm] r342104 - [WebAssembly] Add missing SIMD instruction attributes

[Thomas Lively via llvm-commits]

Author: tlively
Date: Wed Sep 12 19:50:56 2018
New Revision: 342104

URL: http://llvm.org/viewvc/llvm-project?rev=342104&view=rev
Log:
[WebAssembly] Add missing SIMD instruction attributes

Summary:
These attributes are copied from equivalent instructions in
WebAssemblyInstrInfo.td.

Reviewers: aheejin, dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D51518

Modified:
    llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td?rev=342104&r1=342103&r2=342104&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td Wed Sep 12 19:50:56 2018
@@ -19,13 +19,14 @@ foreach SIZE = [2, 4, 8, 16, 32] in
 def LaneIdx#SIZE : ImmLeaf<i32, "return 0 <= Imm && Imm < "#SIZE#";">;
 
 multiclass ConstVec<ValueType vec_t, dag ops, dag pat, string args> {
+  let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1 in
   defm CONST_V128_#vec_t : SIMD_I<(outs V128:$dst), ops, (outs), ops,
                                   [(set V128:$dst, (vec_t pat))],
                                   "v128.const\t$dst, "#args,
                                   "v128.const\t"#args, 0>;
 }
 multiclass SIMDLoad<ValueType vec_t> {
-  let mayLoad = 1 in
+  let mayLoad = 1, isAsCheapAsAMove = 1 in
   defm LOAD_#vec_t :
     SIMD_I<(outs V128:$dst), (ins P2Align:$align, offset32_op:$off, I32:$addr),
            (outs), (ins P2Align:$align, offset32_op:$off), [],
@@ -33,7 +34,7 @@ multiclass SIMDLoad<ValueType vec_t> {
            "v128.load\t$off$align", 1>;
 }
 multiclass SIMDStore<ValueType vec_t> {
-  let mayStore = 1 in
+  let mayStore = 1, isAsCheapAsAMove = 1 in
   defm STORE_#vec_t :
     SIMD_I<(outs), (ins P2Align:$align, offset32_op:$off, I32:$addr, V128:$vec),
            (outs), (ins P2Align:$align, offset32_op:$off), [],