[PATCH] D51932: [AMDGPU] Fix-up cases where writelane has 2 SGPR operands

[David Stuttard via Phabricator via llvm-commits]

dstuttard marked 5 inline comments as done.
dstuttard added inline comments.


================
Comment at: lib/Target/AMDGPU/SIFixSGPRCopies.cpp:457
+
+  for (MachineFunction::iterator BI = MF.begin(), BE = MF.end(); BI != BE;
+       ++BI) {
----------------
rampitec wrote:
> dstuttard wrote:
> > rampitec wrote:
> > > Why cannot you use loop in the runOnMachineFunction()?
> > I think we need all the sgpr to vgpr moves to have been completed before applying this fix since in some cases it might not be necessary.
> > I guess there's an argument for this to be done in a separate pass, or a later pass, then it could go into runOnMachineFunction - any suggestions?
> Given the semantics of writelane it is hard to believe its sources will be moved to VALU. Also if that is going to happen in general, it should have already happened by the time iterator would reach the instruction.
Yes - I think you're right. I've changed it part of the main runOnMachineFunction.


Repository:
  rL LLVM

https://reviews.llvm.org/D51932