[PATCH] D51780: ARM: align loops to 4 bytes on Cortex-M3 and Cortex-M4.

[Tim Northover via Phabricator via llvm-commits]

t.p.northover updated this revision to Diff 165056.
t.p.northover added a comment.

I think I've implemented the suggested changes, except for the function alignment one.

The benchmarks came back as about a 0.2% difference in cycle count, and (crucially) there's no way when deciding function alignment to check for  OptSize so we'd inevitably pessimize some cases.


Repository:
  rL LLVM

https://reviews.llvm.org/D51780

Files:
  llvm/include/llvm/CodeGen/TargetLowering.h
  llvm/lib/CodeGen/MachineBlockPlacement.cpp
  llvm/lib/Target/ARM/ARM.td
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMISelLowering.h
  llvm/lib/Target/ARM/ARMSubtarget.h
  llvm/test/CodeGen/ARM/loop-align-cortex-m.ll

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