[llvm] r341996 - add IR flags to MI
Michael Berg via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 11 14:35:32 PDT 2018
Author: mcberg2017
Date: Tue Sep 11 14:35:32 2018
New Revision: 341996
URL: http://llvm.org/viewvc/llvm-project?rev=341996&view=rev
Log:
add IR flags to MI
Summary: Initial support for nsw, nuw and exact flags in MI
Reviewers: spatel, hfinkel, wristow
Reviewed By: spatel
Subscribers: nlopes
Differential Revision: https://reviews.llvm.org/D51738
Modified:
llvm/trunk/include/llvm/CodeGen/MachineInstr.h
llvm/trunk/lib/CodeGen/MIRParser/MILexer.cpp
llvm/trunk/lib/CodeGen/MIRParser/MILexer.h
llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp
llvm/trunk/lib/CodeGen/MIRPrinter.cpp
llvm/trunk/lib/CodeGen/MachineInstr.cpp
llvm/trunk/test/CodeGen/MIR/X86/copyIRflags.mir
Modified: llvm/trunk/include/llvm/CodeGen/MachineInstr.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstr.h?rev=341996&r1=341995&r2=341996&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineInstr.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineInstr.h Tue Sep 11 14:35:32 2018
@@ -97,8 +97,14 @@ public:
// contraction operations like fma.
FmAfn = 1 << 9, // Instruction may map to Fast math
// instrinsic approximation.
- FmReassoc = 1 << 10 // Instruction supports Fast math
+ FmReassoc = 1 << 10, // Instruction supports Fast math
// reassociation of operand order.
+ NoUWrap = 1 << 11, // Instruction supports binary operator
+ // no unsigned wrap.
+ NoSWrap = 1 << 12, // Instruction supports binary operator
+ // no signed wrap.
+ IsExact = 1 << 13 // Instruction supports division is
+ // known to be exact.
};
private:
Modified: llvm/trunk/lib/CodeGen/MIRParser/MILexer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MILexer.cpp?rev=341996&r1=341995&r2=341996&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRParser/MILexer.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRParser/MILexer.cpp Tue Sep 11 14:35:32 2018
@@ -202,6 +202,9 @@ static MIToken::TokenKind getIdentifierK
.Case("contract", MIToken::kw_contract)
.Case("afn", MIToken::kw_afn)
.Case("reassoc", MIToken::kw_reassoc)
+ .Case("nuw" , MIToken::kw_nuw)
+ .Case("nsw" , MIToken::kw_nsw)
+ .Case("exact" , MIToken::kw_exact)
.Case("debug-location", MIToken::kw_debug_location)
.Case("same_value", MIToken::kw_cfi_same_value)
.Case("offset", MIToken::kw_cfi_offset)
Modified: llvm/trunk/lib/CodeGen/MIRParser/MILexer.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MILexer.h?rev=341996&r1=341995&r2=341996&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRParser/MILexer.h (original)
+++ llvm/trunk/lib/CodeGen/MIRParser/MILexer.h Tue Sep 11 14:35:32 2018
@@ -71,6 +71,9 @@ struct MIToken {
kw_contract,
kw_afn,
kw_reassoc,
+ kw_nuw,
+ kw_nsw,
+ kw_exact,
kw_debug_location,
kw_cfi_same_value,
kw_cfi_offset,
Modified: llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp?rev=341996&r1=341995&r2=341996&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp Tue Sep 11 14:35:32 2018
@@ -963,7 +963,10 @@ bool MIParser::parseInstruction(unsigned
Token.is(MIToken::kw_arcp) ||
Token.is(MIToken::kw_contract) ||
Token.is(MIToken::kw_afn) ||
- Token.is(MIToken::kw_reassoc)) {
+ Token.is(MIToken::kw_reassoc) ||
+ Token.is(MIToken::kw_nuw) ||
+ Token.is(MIToken::kw_nsw) ||
+ Token.is(MIToken::kw_exact)) {
// Mine frame and fast math flags
if (Token.is(MIToken::kw_frame_setup))
Flags |= MachineInstr::FrameSetup;
@@ -983,6 +986,12 @@ bool MIParser::parseInstruction(unsigned
Flags |= MachineInstr::FmAfn;
if (Token.is(MIToken::kw_reassoc))
Flags |= MachineInstr::FmReassoc;
+ if (Token.is(MIToken::kw_nuw))
+ Flags |= MachineInstr::NoUWrap;
+ if (Token.is(MIToken::kw_nsw))
+ Flags |= MachineInstr::NoSWrap;
+ if (Token.is(MIToken::kw_exact))
+ Flags |= MachineInstr::IsExact;
lex();
}
Modified: llvm/trunk/lib/CodeGen/MIRPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRPrinter.cpp?rev=341996&r1=341995&r2=341996&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRPrinter.cpp Tue Sep 11 14:35:32 2018
@@ -695,6 +695,12 @@ void MIPrinter::print(const MachineInstr
OS << "afn ";
if (MI.getFlag(MachineInstr::FmReassoc))
OS << "reassoc ";
+ if (MI.getFlag(MachineInstr::NoUWrap))
+ OS << "nuw ";
+ if (MI.getFlag(MachineInstr::NoSWrap))
+ OS << "nsw ";
+ if (MI.getFlag(MachineInstr::IsExact))
+ OS << "exact ";
OS << TII->getName(MI.getOpcode());
if (I < E)
Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=341996&r1=341995&r2=341996&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Tue Sep 11 14:35:32 2018
@@ -1479,6 +1479,12 @@ void MachineInstr::print(raw_ostream &OS
OS << "afn ";
if (getFlag(MachineInstr::FmReassoc))
OS << "reassoc ";
+ if (getFlag(MachineInstr::NoUWrap))
+ OS << "nuw ";
+ if (getFlag(MachineInstr::NoSWrap))
+ OS << "nsw ";
+ if (getFlag(MachineInstr::IsExact))
+ OS << "exact ";
// Print the opcode name.
if (TII)
Modified: llvm/trunk/test/CodeGen/MIR/X86/copyIRflags.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/copyIRflags.mir?rev=341996&r1=341995&r2=341996&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/copyIRflags.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/copyIRflags.mir Tue Sep 11 14:35:32 2018
@@ -8,11 +8,12 @@ body: |
bb.0.entry:
liveins: $eax
- $eax = ADD32rr $eax, killed $eax, implicit-def dead $eflags
- ; CHECK: $eax = ADD32rr $eax, killed $eax, implicit-def dead $eflags
- $eax = ADD32rr $eax, killed $eax, implicit-def dead $eflags
- ; CHECK: $eax = SAR32ri $eax, 1, implicit-def dead $eflags
- $eax = SAR32ri $eax, 1, implicit-def dead $eflags
+ ; CHECK: $eax = nsw ADD32rr $eax, killed $eax, implicit-def dead $eflags
+ $eax = nsw ADD32rr $eax, killed $eax, implicit-def dead $eflags
+ ; CHECK: $eax = nuw ADD32rr $eax, killed $eax, implicit-def dead $eflags
+ $eax = nuw ADD32rr $eax, killed $eax, implicit-def dead $eflags
+ ; CHECK: $eax = exact SAR32ri $eax, 1, implicit-def dead $eflags
+ $eax = exact SAR32ri $eax, 1, implicit-def dead $eflags
; CHECK: RET 0, $eax
RET 0, $eax
More information about the llvm-commits
mailing list