[PATCH] D51932: [AMDGPU] Fix-up cases where writelane has 2 SGPR operands
David Stuttard via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 11 07:40:33 PDT 2018
dstuttard created this revision.
Herald added subscribers: llvm-commits, t-tye, tpr, yaxunl, mgorny, nhaehnle, wdng, jvesely, kzhuravl, arsenm.
Even though writelane doesn't have the same constraints as other valu
instructions it still can't violate the >1 SGPR operand constraint
Due to later register propagation (e.g. fixing up vgpr operands via
readfirstlane) changing writelane to only have a single SGPR is tricky.
This implementation puts a new check after SIFixSGPRCopies that prevents
multiple SGPRs being used in any writelane instructions.
The algorithm used is to check for trivial copy prop of suitable constants into
one of the SGPR operands and perform that if possible. If this isn't possible
put an explicit copy of Src1 SGPR into M0 and use that instead (this is
allowable for writelane as the constraint is for SGPR read-port and not
constant-bus access).
Repository:
rL LLVM
https://reviews.llvm.org/D51932
Files:
lib/Target/AMDGPU/SIFixSGPRCopies.cpp
lib/Target/AMDGPU/SIPeepholeSDWA.cpp
lib/Target/AMDGPU/Utils/AMDGPUMCUtils.cpp
lib/Target/AMDGPU/Utils/AMDGPUMCUtils.h
lib/Target/AMDGPU/Utils/CMakeLists.txt
test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
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