[PATCH] D51927: [ARM] Enable spilling of the hGPR class in Thumb2

[Petr Pavlu via Phabricator via llvm-commits]

petpav01 created this revision.
petpav01 added reviewers: eli.friedman, t.p.northover.
Herald added subscribers: llvm-commits, chrib, kristof.beyls, qcolombet.
Herald added a reviewer: javed.absar.

Note: This patch solves a similar problem as https://reviews.llvm.org/D49364. The difference is that this change addresses the problem in Thumb2 while https://reviews.llvm.org/D49364 is for Thumb1.

LLVM fails with an assertion error or generates incorrect code (if assertions are disabled) when a register of the `hGPR` class needs to be spilled in Thumb2.

Example:

  $ cat test.c
  void constraint_h(void) {
    int i;
    asm volatile("@ %0" : : "h" (i) : "r12");
  }
  $ clang -target arm-none-eabi -march=armv7-m -c test.c
  Unsupported addressing mode!
  UNREACHABLE executed at /work/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp:630!
  [...]

The code was compiled at `-O0` and so Fast Register Allocator is used. The allocator ends up calling `Thumb2InstrInfo::storeRegToStackSlot()` to store r12 (`hGPR`) in a stack slot but the method does not know how to do it. The request then gets deferred to `ARMBaseInstrInfo::storeRegToStackSlot()` which incorrectly generates ARM instruction `STRi12` for the store. If assertions are enabled, this gets caught later in `rewriteT2FrameIndex()` because the instruction uses `ARMII::AddrMode_i12` and the rewrite function does not know how to handle it.

The patch generalizes code in `Thumb2InstrInfo::storeRegToStackSlot()` and `loadRegToStackSlot()` to allow the `GPR` class or any of its sub-classes (including `hGPR`) to be stored/loaded by `ARM::t2STRi12`/`ARM::t2LDRi12`.


Repository:
  rL LLVM

https://reviews.llvm.org/D51927

Files:
  lib/Target/ARM/Thumb2InstrInfo.cpp
  test/CodeGen/Thumb2/high-reg-spill.mir


Index: test/CodeGen/Thumb2/high-reg-spill.mir
===================================================================
--- /dev/null
+++ test/CodeGen/Thumb2/high-reg-spill.mir
@@ -0,0 +1,50 @@
+# RUN: llc -run-pass regallocfast %s -o - | FileCheck %s
+
+# This test examines register allocation and spilling with Fast Register
+# Allocator. The test uses inline assembler that requests an input variable to
+# be loaded in a high register but at the same time has r12 marked as clobbered.
+# The allocator initially satisfies the load request by selecting r12 but then
+# needs to spill this register when it reaches the INLINEASM instruction and
+# notices its clobber definition.
+#
+# The test checks that the compiler is able to spill a register from the hGPR
+# class in Thumb2 by inserting the t2STRi12/t2LDRi12 instructions.
+
+--- |
+  ; ModuleID = 'test.ll'
+  source_filename = "test.c"
+  target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
+  target triple = "thumbv7m-none-unknown-eabi"
+
+  define dso_local void @constraint_h() {
+  entry:
+    %i = alloca i32, align 4
+    %0 = load i32, i32* %i, align 4
+    call void asm sideeffect "@ $0", "h,~{r12}"(i32 %0)
+    ret void
+  }
+
+...
+---
+name:            constraint_h
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: hgpr }
+  - { id: 1, class: tgpr }
+stack:
+  - { id: 0, name: i, size: 4, alignment: 4, stack-id: 0, local-offset: -4 }
+body:             |
+  bb.0.entry:
+    %1:tgpr = tLDRspi %stack.0.i, 0, 14, $noreg :: (dereferenceable load 4 from %ir.i)
+    %0:hgpr = COPY %1
+    INLINEASM &"@ $0", 1, 589833, %0, 12, implicit-def early-clobber $r12
+    tBX_RET 14, $noreg
+
+...
+# CHECK: bb.0.entry:
+# CHECK-NEXT: renamable $r0 = tLDRspi %stack.0.i, 0, 14, $noreg :: (dereferenceable load 4 from %ir.i)
+# CHECK-NEXT: renamable $r12 = COPY killed renamable $r0
+# CHECK-NEXT: t2STRi12 killed $r12, %stack.1, 0, 14, $noreg :: (store 4 into %stack.1)
+# CHECK-NEXT: $r8 = t2LDRi12 %stack.1, 0, 14, $noreg :: (load 4 from %stack.1)
+# CHECK-NEXT: INLINEASM &"@ $0", 1, 589833, killed renamable $r8, 12, implicit-def early-clobber $r12
+# CHECK-NEXT: tBX_RET 14, $noreg
Index: lib/Target/ARM/Thumb2InstrInfo.cpp
===================================================================
--- lib/Target/ARM/Thumb2InstrInfo.cpp
+++ lib/Target/ARM/Thumb2InstrInfo.cpp
@@ -146,9 +146,7 @@
       MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore,
       MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
 
-  if (RC == &ARM::GPRRegClass   || RC == &ARM::tGPRRegClass ||
-      RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass ||
-      RC == &ARM::GPRnopcRegClass) {
+  if (ARM::GPRRegClass.hasSubClassEq(RC)) {
     BuildMI(MBB, I, DL, get(ARM::t2STRi12))
         .addReg(SrcReg, getKillRegState(isKill))
         .addFrameIndex(FI)
@@ -190,9 +188,7 @@
   DebugLoc DL;
   if (I != MBB.end()) DL = I->getDebugLoc();
 
-  if (RC == &ARM::GPRRegClass   || RC == &ARM::tGPRRegClass ||
-      RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass ||
-      RC == &ARM::GPRnopcRegClass) {
+  if (ARM::GPRRegClass.hasSubClassEq(RC)) {
     BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
         .addFrameIndex(FI)
         .addImm(0)


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