[PATCH] D51773: [mips] Add a pattern for 64-bit GPR variant of the `rdhwr` instruction

[Simon Atanasyan via Phabricator via llvm-commits]

This revision was not accepted when it landed; it landed in state "Needs Review".
This revision was automatically updated to reflect the committed changes.
Closed by commit rL341919: [mips] Add a pattern for 64-bit GPR variant of the `rdhwr` instruction (authored by atanasyan, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D51773?vs=164364&id=164831#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D51773

Files:
  llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
  llvm/trunk/test/CodeGen/Mips/tls.ll


Index: llvm/trunk/test/CodeGen/Mips/tls.ll
===================================================================
--- llvm/trunk/test/CodeGen/Mips/tls.ll
+++ llvm/trunk/test/CodeGen/Mips/tls.ll
@@ -48,14 +48,14 @@
 ; STATIC32-LABEL:   f1:
 ; STATIC32:   lui     $[[R0:[0-9]+]], %tprel_hi(t1)
 ; STATIC32:   addiu   $[[R1:[0-9]+]], $[[R0]], %tprel_lo(t1)
-; STATIC32:   rdhwr   $3, $29
+; STATIC32:   rdhwr   $3, $29{{$}}
 ; STATIC32:   addu    $[[R2:[0-9]+]], $3, $[[R1]]
 ; STATIC32:   lw      $2, 0($[[R2]])
 
 ; STATIC64-LABEL:   f1:
 ; STATIC64:   lui     $[[R0:[0-9]+]], %tprel_hi(t1)
 ; STATIC64:   daddiu  $[[R1:[0-9]+]], $[[R0]], %tprel_lo(t1)
-; STATIC64:   rdhwr   $3, $29, 0
+; STATIC64:   rdhwr   $3, $29{{$}}
 ; STATIC64:   daddu   $[[R2:[0-9]+]], $3, $[[R0]]
 ; STATIC64:   lw      $2, 0($[[R2]])
 }
@@ -101,15 +101,15 @@
 ; STATIC32-LABEL:   f2:
 ; STATIC32:   lui     $[[R0:[0-9]+]], %hi(__gnu_local_gp)
 ; STATIC32:   addiu   $[[GP:[0-9]+]], $[[R0]], %lo(__gnu_local_gp)
-; STATIC32:   rdhwr   $3, $29
+; STATIC32:   rdhwr   $3, $29{{$}}
 ; STATIC32:   lw      $[[R0:[0-9]+]], %gottprel(t2)($[[GP]])
 ; STATIC32:   addu    $[[R1:[0-9]+]], $3, $[[R0]]
 ; STATIC32:   lw      $2, 0($[[R1]])
 
 ; STATIC64-LABEL:   f2:
 ; STATIC64:   lui     $[[R0:[0-9]+]], %hi(%neg(%gp_rel(f2)))
 ; STATIC64:   daddiu  $[[GP:[0-9]+]], $[[R0]], %lo(%neg(%gp_rel(f2)))
-; STATIC64:   rdhwr   $3, $29
+; STATIC64:   rdhwr   $3, $29{{$}}
 ; STATIC64:   ld      $[[R0:[0-9]+]], %gottprel(t2)($[[GP]])
 ; STATIC64:   daddu   $[[R1:[0-9]+]], $3, $[[R0]]
 ; STATIC64:   lw      $2, 0($[[R1]])
Index: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
===================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
@@ -1139,3 +1139,6 @@
                                   "sltu\t$rs, $rt, $imm">, GPR_64;
 def : MipsInstAlias<"sltu\t$rs, $imm", (SLTUImm64 GPR64Opnd:$rs, GPR64Opnd:$rs,
                                                   imm64:$imm)>, GPR_64;
+
+def : MipsInstAlias<"rdhwr $rt, $rs",
+                    (RDHWR64 GPR64Opnd:$rt, HWRegsOpnd:$rs, 0), 1>, GPR_64;


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D51773.164831.patch
Type: text/x-patch
Size: 2164 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20180911/88e77fbb/attachment.bin>