[PATCH] D51873: [AArch64] Add support for the ABS dag node and testcases for integer abs.

[Ivan Kulagin via Phabricator via llvm-commits]

ikulagin created this revision.
ikulagin added reviewers: t.p.northover, spatel, kparzysz, RKSimon.
Herald added a reviewer: javed.absar.
Herald added subscribers: llvm-commits, kristof.beyls.

Indicate that the ABS is legal for the i64 type when the NEON is supported.

These changes are related to https://reviews.llvm.org/D49837.


Repository:
  rL LLVM

https://reviews.llvm.org/D51873

Files:
  lib/Target/AArch64/AArch64ISelLowering.cpp
  test/CodeGen/AArch64/iabs.ll


Index: test/CodeGen/AArch64/iabs.ll
===================================================================
--- /dev/null
+++ test/CodeGen/AArch64/iabs.ll
@@ -0,0 +1,53 @@
+; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
+
+define i8 @test_i8(i8 %a) nounwind {
+; CHECK-LABEL: test_i8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:       sxtb w8, w0
+; CHECK-NEXT:       cmp w8, #0
+; CHECK-NEXT:       cneg w0, w8, mi
+; CHECK-NEXT:       ret
+  %tmp1neg = sub i8 0, %a
+  %b = icmp sgt i8 %a, -1
+  %abs = select i1 %b, i8 %a, i8 %tmp1neg
+  ret i8 %abs
+}
+
+define i16 @test_i16(i16 %a) nounwind {
+; CHECK-LABEL: test_i16:
+; CHECK:  // %bb.0:
+; CHECK-NEXT:  sxth w8, w0
+; CHECK-NEXT:  cmp w8, #0
+; CHECK-NEXT:  cneg w0, w8, mi
+; CHECK-NEXT:  ret
+  %tmp1neg = sub i16 0, %a
+  %b = icmp sgt i16 %a, -1
+  %abs = select i1 %b, i16 %a, i16 %tmp1neg
+  ret i16 %abs
+}
+
+define i32 @test_i32(i32 %a) nounwind {
+; CHECK-LABEL: test_i32:
+; CHECK:  // %bb.0:
+; CHECK-NEXT:  cmp w0, #0
+; CHECK-NEXT:  cneg w0, w0, mi
+; CHECK-NEXT:  ret
+  %tmp1neg = sub i32 0, %a
+  %b = icmp sgt i32 %a, -1
+  %abs = select i1 %b, i32 %a, i32 %tmp1neg
+  ret i32 %abs
+}
+
+define i64 @test_i64(i64 %a) nounwind {
+; CHECK-LABEL: test_i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:  fmov d0, x0
+; CHECK-NEXT:  abs d0, d0
+; CHECK-NEXT:  fmov x0, d0
+; CHECK-NEXT:  ret
+  %tmp1neg = sub i64 0, %a
+  %b = icmp sgt i64 %a, -1
+  %abs = select i1 %b, i64 %a, i64 %tmp1neg
+  ret i64 %abs
+}
+
Index: lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- lib/Target/AArch64/AArch64ISelLowering.cpp
+++ lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -156,6 +156,10 @@
     addQRTypeForNEON(MVT::v4i32);
     addQRTypeForNEON(MVT::v2i64);
     addQRTypeForNEON(MVT::v8f16);
+
+    // The AArch64 SIMD extension supports the scalar variant
+    // of the ABS instruction.
+    setOperationAction(ISD::ABS, MVT::i64, Legal);
   }
 
   // Compute derived properties from the register classes


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D51873.164707.patch
Type: text/x-patch
Size: 2059 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20180910/c1fbbb39/attachment.bin>