[llvm] r341752 - [X86] Mark the ADCX and ADOX instruction as commutable.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Sep 8 11:47:56 PDT 2018
Author: ctopper
Date: Sat Sep 8 11:47:56 2018
New Revision: 341752
URL: http://llvm.org/viewvc/llvm-project?rev=341752&view=rev
Log:
[X86] Mark the ADCX and ADOX instruction as commutable.
Modified:
llvm/trunk/lib/Target/X86/X86InstrArithmetic.td
llvm/trunk/test/CodeGen/X86/adx-commute.mir
llvm/trunk/test/CodeGen/X86/pr32282.ll
llvm/trunk/test/CodeGen/X86/pr32284.ll
Modified: llvm/trunk/lib/Target/X86/X86InstrArithmetic.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrArithmetic.td?rev=341752&r1=341751&r2=341752&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrArithmetic.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrArithmetic.td Sat Sep 8 11:47:56 2018
@@ -1309,7 +1309,7 @@ let Predicates = [HasBMI2] in {
//
let Predicates = [HasADX], Defs = [EFLAGS], Uses = [EFLAGS],
Constraints = "$src1 = $dst", AddedComplexity = 10 in {
- let SchedRW = [WriteADC] in {
+ let SchedRW = [WriteADC], isCommutable = 1 in {
def ADCX32rr : I<0xF6, MRMSrcReg, (outs GR32:$dst),
(ins GR32:$src1, GR32:$src2),
"adcx{l}\t{$src2, $dst|$dst, $src2}",
Modified: llvm/trunk/test/CodeGen/X86/adx-commute.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/adx-commute.mir?rev=341752&r1=341751&r2=341752&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/adx-commute.mir (original)
+++ llvm/trunk/test/CodeGen/X86/adx-commute.mir Sat Sep 8 11:47:56 2018
@@ -81,8 +81,7 @@ body: |
; CHECK: [[COPY2:%[0-9]+]]:gr32 = COPY $esi
; CHECK: [[COPY3:%[0-9]+]]:gr32 = COPY $edi
; CHECK: dead [[COPY3]].sub_8bit:gr32 = ADD8ri [[COPY3]].sub_8bit, -1, implicit-def $eflags
- ; CHECK: [[COPY4:%[0-9]+]]:gr32 = COPY [[COPY2]]
- ; CHECK: [[ADCX32rr:%[0-9]+]]:gr32 = ADCX32rr [[ADCX32rr]], [[COPY1]], implicit-def dead $eflags, implicit killed $eflags
+ ; CHECK: [[ADCX32rr:%[0-9]+]]:gr32 = ADCX32rr [[ADCX32rr]], [[COPY2]], implicit-def dead $eflags, implicit killed $eflags
; CHECK: [[IMUL32rr:%[0-9]+]]:gr32 = IMUL32rr [[IMUL32rr]], [[COPY2]], implicit-def dead $eflags
; CHECK: MOV32mr [[COPY]], 1, $noreg, 0, $noreg, [[IMUL32rr]] :: (store 4 into %ir.res)
; CHECK: RET 0
@@ -127,8 +126,7 @@ body: |
; CHECK: [[COPY2:%[0-9]+]]:gr64 = COPY $rsi
; CHECK: [[COPY3:%[0-9]+]]:gr32 = COPY $edi
; CHECK: dead [[COPY3]].sub_8bit:gr32 = ADD8ri [[COPY3]].sub_8bit, -1, implicit-def $eflags
- ; CHECK: [[COPY4:%[0-9]+]]:gr64 = COPY [[COPY2]]
- ; CHECK: [[ADCX64rr:%[0-9]+]]:gr64 = ADCX64rr [[ADCX64rr]], [[COPY1]], implicit-def dead $eflags, implicit killed $eflags
+ ; CHECK: [[ADCX64rr:%[0-9]+]]:gr64 = ADCX64rr [[ADCX64rr]], [[COPY2]], implicit-def dead $eflags, implicit killed $eflags
; CHECK: [[IMUL64rr:%[0-9]+]]:gr64 = IMUL64rr [[IMUL64rr]], [[COPY2]], implicit-def dead $eflags
; CHECK: MOV64mr [[COPY]], 1, $noreg, 0, $noreg, [[IMUL64rr]] :: (store 8 into %ir.res)
; CHECK: RET 0
@@ -173,8 +171,7 @@ body: |
; CHECK: [[COPY2:%[0-9]+]]:gr32 = COPY $esi
; CHECK: [[COPY3:%[0-9]+]]:gr32 = COPY $edi
; CHECK: dead [[COPY3]].sub_8bit:gr32 = ADD8ri [[COPY3]].sub_8bit, 127, implicit-def $eflags
- ; CHECK: [[COPY4:%[0-9]+]]:gr32 = COPY [[COPY2]]
- ; CHECK: [[ADOX32rr:%[0-9]+]]:gr32 = ADOX32rr [[ADOX32rr]], [[COPY1]], implicit-def dead $eflags, implicit killed $eflags
+ ; CHECK: [[ADOX32rr:%[0-9]+]]:gr32 = ADOX32rr [[ADOX32rr]], [[COPY2]], implicit-def dead $eflags, implicit killed $eflags
; CHECK: [[IMUL32rr:%[0-9]+]]:gr32 = IMUL32rr [[IMUL32rr]], [[COPY2]], implicit-def dead $eflags
; CHECK: MOV32mr [[COPY]], 1, $noreg, 0, $noreg, [[IMUL32rr]] :: (store 4 into %ir.res)
; CHECK: RET 0
@@ -219,8 +216,7 @@ body: |
; CHECK: [[COPY2:%[0-9]+]]:gr64 = COPY $rsi
; CHECK: [[COPY3:%[0-9]+]]:gr32 = COPY $edi
; CHECK: dead [[COPY3]].sub_8bit:gr32 = ADD8ri [[COPY3]].sub_8bit, 127, implicit-def $eflags
- ; CHECK: [[COPY4:%[0-9]+]]:gr64 = COPY [[COPY2]]
- ; CHECK: [[ADOX64rr:%[0-9]+]]:gr64 = ADOX64rr [[ADOX64rr]], [[COPY1]], implicit-def dead $eflags, implicit killed $eflags
+ ; CHECK: [[ADOX64rr:%[0-9]+]]:gr64 = ADOX64rr [[ADOX64rr]], [[COPY2]], implicit-def dead $eflags, implicit killed $eflags
; CHECK: [[IMUL64rr:%[0-9]+]]:gr64 = IMUL64rr [[IMUL64rr]], [[COPY2]], implicit-def dead $eflags
; CHECK: MOV64mr [[COPY]], 1, $noreg, 0, $noreg, [[IMUL64rr]] :: (store 8 into %ir.res)
; CHECK: RET 0
Modified: llvm/trunk/test/CodeGen/X86/pr32282.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr32282.ll?rev=341752&r1=341751&r2=341752&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr32282.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pr32282.ll Sat Sep 8 11:47:56 2018
@@ -25,8 +25,8 @@ define void @foo() {
; X86-NEXT: andl $-2, %eax
; X86-NEXT: xorl %edx, %edx
; X86-NEXT: addl $7, %eax
-; X86-NEXT: adcxl %edx, %ecx
-; X86-NEXT: pushl %ecx
+; X86-NEXT: adcxl %ecx, %edx
+; X86-NEXT: pushl %edx
; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl %eax
; X86-NEXT: .cfi_adjust_cfa_offset 4
Modified: llvm/trunk/test/CodeGen/X86/pr32284.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr32284.ll?rev=341752&r1=341751&r2=341752&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr32284.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pr32284.ll Sat Sep 8 11:47:56 2018
@@ -268,9 +268,9 @@ define void @f1() {
; 686-NEXT: sete %cl
; 686-NEXT: xorl %edi, %edi
; 686-NEXT: addl $7093, %edx # imm = 0x1BB5
-; 686-NEXT: adcxl %edi, %esi
+; 686-NEXT: adcxl %esi, %edi
; 686-NEXT: cmpl %ecx, %edx
-; 686-NEXT: sbbl $0, %esi
+; 686-NEXT: sbbl $0, %edi
; 686-NEXT: setl %cl
; 686-NEXT: movzbl %cl, %ecx
; 686-NEXT: movl %ecx, var_57
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