[llvm] r341705 - [X86] Don't create ZERO_EXTEND_INREG/SIGN_EXTEND_INREG for v1iX vectors.

[Craig Topper via llvm-commits]

Author: ctopper
Date: Fri Sep  7 13:56:03 2018
New Revision: 341705

URL: http://llvm.org/viewvc/llvm-project?rev=341705&view=rev
Log:
[X86] Don't create ZERO_EXTEND_INREG/SIGN_EXTEND_INREG for v1iX vectors.

The generic type legalizer will scalarize vXi1 instructions getting rid of the vector entirely. Creating wider vector instructions is just going to prevent that.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/test/CodeGen/X86/avg.ll
    llvm/trunk/test/CodeGen/X86/vec_cast.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=341705&r1=341704&r2=341705&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Sep  7 13:56:03 2018
@@ -38180,7 +38180,7 @@ static SDValue combineToExtendVectorInRe
   EVT InSVT = InVT.getScalarType();
 
   // Input type must be a vector and we must be extending legal integer types.
-  if (!VT.isVector())
+  if (!VT.isVector() || VT.getVectorNumElements() < 2)
     return SDValue();
   if (SVT != MVT::i64 && SVT != MVT::i32 && SVT != MVT::i16)
     return SDValue();

Modified: llvm/trunk/test/CodeGen/X86/avg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avg.ll?rev=341705&r1=341704&r2=341705&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avg.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avg.ll Fri Sep  7 13:56:03 2018
@@ -2901,15 +2901,8 @@ define void @not_avg_v16i8_wide_constant
 define <1 x i8> @avg_v1i8(<1 x i8> %x, <1 x i8> %y) {
 ; SSE2-LABEL: avg_v1i8:
 ; SSE2:       # %bb.0:
-; SSE2-NEXT:    movd %edi, %xmm0
-; SSE2-NEXT:    pxor %xmm1, %xmm1
-; SSE2-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
-; SSE2-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; SSE2-NEXT:    movd %xmm0, %eax
-; SSE2-NEXT:    movd %esi, %xmm0
-; SSE2-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
-; SSE2-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; SSE2-NEXT:    movd %xmm0, %ecx
+; SSE2-NEXT:    movzbl %dil, %eax
+; SSE2-NEXT:    movzbl %sil, %ecx
 ; SSE2-NEXT:    leal 1(%rax,%rcx), %eax
 ; SSE2-NEXT:    shrl %eax
 ; SSE2-NEXT:    # kill: def $al killed $al killed $eax
@@ -2917,12 +2910,8 @@ define <1 x i8> @avg_v1i8(<1 x i8> %x, <
 ;
 ; AVX-LABEL: avg_v1i8:
 ; AVX:       # %bb.0:
-; AVX-NEXT:    vmovd %edi, %xmm0
-; AVX-NEXT:    vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
-; AVX-NEXT:    vmovd %xmm0, %eax
-; AVX-NEXT:    vmovd %esi, %xmm0
-; AVX-NEXT:    vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
-; AVX-NEXT:    vmovd %xmm0, %ecx
+; AVX-NEXT:    movzbl %dil, %eax
+; AVX-NEXT:    movzbl %sil, %ecx
 ; AVX-NEXT:    leal 1(%rax,%rcx), %eax
 ; AVX-NEXT:    shrl %eax
 ; AVX-NEXT:    # kill: def $al killed $al killed $eax

Modified: llvm/trunk/test/CodeGen/X86/vec_cast.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_cast.ll?rev=341705&r1=341704&r2=341705&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_cast.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_cast.ll Fri Sep  7 13:56:03 2018
@@ -53,19 +53,12 @@ define <3 x i32> @b(<3 x i16> %a) nounwi
 define <1 x i32> @c(<1 x i16> %a) nounwind {
 ; CHECK-LIN-LABEL: c:
 ; CHECK-LIN:       # %bb.0:
-; CHECK-LIN-NEXT:    movd %edi, %xmm0
-; CHECK-LIN-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[0,0,2,1,4,5,6,7]
-; CHECK-LIN-NEXT:    psrad $16, %xmm0
-; CHECK-LIN-NEXT:    movd %xmm0, %eax
+; CHECK-LIN-NEXT:    movswl %di, %eax
 ; CHECK-LIN-NEXT:    retq
 ;
 ; CHECK-WIN-LABEL: c:
 ; CHECK-WIN:       # %bb.0:
-; CHECK-WIN-NEXT:    # kill: def $cx killed $cx def $ecx
-; CHECK-WIN-NEXT:    movd %ecx, %xmm0
-; CHECK-WIN-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[0,0,2,1,4,5,6,7]
-; CHECK-WIN-NEXT:    psrad $16, %xmm0
-; CHECK-WIN-NEXT:    movd %xmm0, %eax
+; CHECK-WIN-NEXT:    movswl %cx, %eax
 ; CHECK-WIN-NEXT:    retq
   %c = sext <1 x i16> %a to <1 x i32>
   ret <1 x i32> %c
@@ -120,19 +113,12 @@ define <3 x i32> @e(<3 x i16> %a) nounwi
 define <1 x i32> @f(<1 x i16> %a) nounwind {
 ; CHECK-LIN-LABEL: f:
 ; CHECK-LIN:       # %bb.0:
-; CHECK-LIN-NEXT:    movd %edi, %xmm0
-; CHECK-LIN-NEXT:    pxor %xmm1, %xmm1
-; CHECK-LIN-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; CHECK-LIN-NEXT:    movd %xmm0, %eax
+; CHECK-LIN-NEXT:    movzwl %di, %eax
 ; CHECK-LIN-NEXT:    retq
 ;
 ; CHECK-WIN-LABEL: f:
 ; CHECK-WIN:       # %bb.0:
-; CHECK-WIN-NEXT:    # kill: def $cx killed $cx def $ecx
-; CHECK-WIN-NEXT:    movd %ecx, %xmm0
-; CHECK-WIN-NEXT:    pxor %xmm1, %xmm1
-; CHECK-WIN-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; CHECK-WIN-NEXT:    movd %xmm0, %eax
+; CHECK-WIN-NEXT:    movzwl %cx, %eax
 ; CHECK-WIN-NEXT:    retq
   %c = zext <1 x i16> %a to <1 x i32>
   ret <1 x i32> %c