[llvm] r341652 - [DAGCombiner] foldBitcastedFPLogic - Add basic vector support
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 7 05:13:45 PDT 2018
Author: rksimon
Date: Fri Sep 7 05:13:45 2018
New Revision: 341652
URL: http://llvm.org/viewvc/llvm-project?rev=341652&view=rev
Log:
[DAGCombiner] foldBitcastedFPLogic - Add basic vector support
Add support for bitcasts from float type to an integer type of the same element bitwidth.
There maybe cases where we need to support different widths (e.g. as SSE __m128i is treated as v2i64) - but I haven't seen cases of this in the wild yet.
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/trunk/test/CodeGen/X86/fp-logic.ll
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=341652&r1=341651&r2=341652&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Sep 7 05:13:45 2018
@@ -9777,11 +9777,11 @@ static SDValue foldBitcastedFPLogic(SDNo
if (!VT.isFloatingPoint() || !TLI.hasBitPreservingFPLogic(VT))
return SDValue();
- // TODO: Use splat values for the constant-checking below and remove this
- // restriction.
+ // TODO: Handle cases where the integer constant is a different scalar
+ // bitwidth to the FP.
SDValue N0 = N->getOperand(0);
EVT SourceVT = N0.getValueType();
- if (SourceVT.isVector())
+ if (VT.getScalarSizeInBits() != SourceVT.getScalarSizeInBits())
return SDValue();
unsigned FPOpcode;
@@ -9789,11 +9789,11 @@ static SDValue foldBitcastedFPLogic(SDNo
switch (N0.getOpcode()) {
case ISD::AND:
FPOpcode = ISD::FABS;
- SignMask = ~APInt::getSignMask(SourceVT.getSizeInBits());
+ SignMask = ~APInt::getSignMask(SourceVT.getScalarSizeInBits());
break;
case ISD::XOR:
FPOpcode = ISD::FNEG;
- SignMask = APInt::getSignMask(SourceVT.getSizeInBits());
+ SignMask = APInt::getSignMask(SourceVT.getScalarSizeInBits());
break;
// TODO: ISD::OR --> ISD::FNABS?
default:
@@ -9803,11 +9803,11 @@ static SDValue foldBitcastedFPLogic(SDNo
// Fold (bitcast int (and (bitcast fp X to int), 0x7fff...) to fp) -> fabs X
// Fold (bitcast int (xor (bitcast fp X to int), 0x8000...) to fp) -> fneg X
SDValue LogicOp0 = N0.getOperand(0);
- ConstantSDNode *LogicOp1 = dyn_cast<ConstantSDNode>(N0.getOperand(1));
+ ConstantSDNode *LogicOp1 = isConstOrConstSplat(N0.getOperand(1));
if (LogicOp1 && LogicOp1->getAPIntValue() == SignMask &&
LogicOp0.getOpcode() == ISD::BITCAST &&
- LogicOp0->getOperand(0).getValueType() == VT)
- return DAG.getNode(FPOpcode, SDLoc(N), VT, LogicOp0->getOperand(0));
+ LogicOp0.getOperand(0).getValueType() == VT)
+ return DAG.getNode(FPOpcode, SDLoc(N), VT, LogicOp0.getOperand(0));
return SDValue();
}
Modified: llvm/trunk/test/CodeGen/X86/fp-logic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fp-logic.ll?rev=341652&r1=341651&r2=341652&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fp-logic.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fp-logic.ll Fri Sep 7 05:13:45 2018
@@ -311,8 +311,7 @@ define float @fsub_bitcast_fneg(float %x
define <4 x float> @fadd_bitcast_fneg_vec(<4 x float> %x, <4 x float> %y) {
; CHECK-LABEL: fadd_bitcast_fneg_vec:
; CHECK: # %bb.0:
-; CHECK-NEXT: xorps {{.*}}(%rip), %xmm1
-; CHECK-NEXT: addps %xmm1, %xmm0
+; CHECK-NEXT: subps %xmm1, %xmm0
; CHECK-NEXT: retq
%bc1 = bitcast <4 x float> %y to <4 x i32>
%xor = xor <4 x i32> %bc1, <i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648>
@@ -324,8 +323,7 @@ define <4 x float> @fadd_bitcast_fneg_ve
define <4 x float> @fsub_bitcast_fneg_vec(<4 x float> %x, <4 x float> %y) {
; CHECK-LABEL: fsub_bitcast_fneg_vec:
; CHECK: # %bb.0:
-; CHECK-NEXT: xorps {{.*}}(%rip), %xmm1
-; CHECK-NEXT: subps %xmm1, %xmm0
+; CHECK-NEXT: addps %xmm1, %xmm0
; CHECK-NEXT: retq
%bc1 = bitcast <4 x float> %y to <4 x i32>
%xor = xor <4 x i32> %bc1, <i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648>
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