[PATCH] D50222: [CodeGen] [SelectionDAG] More efficient code for X % C == 0 (UREM case)

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added a comment.

In https://reviews.llvm.org/D50222#1221943, @RKSimon wrote:

> Please add uniform and non-uniform vector test cases as well.




In https://reviews.llvm.org/D50222#1223180, @xbolva00 wrote:

> And according to GCC mailing list (https://gcc.gnu.org/ml/gcc-patches/2018-09/msg00193.html) and their stats,  unsigned case of X % C1 == C2 is still worth to handle as well.


@hermord to reiterate, as far i'm concerned, **this** only needs vector tests.
Everything else //should// go into new reviews (srem, urem nonsplat, srem nonsplat; non-zero constants (another 4 reviews ideally?)
As for the vector tests, just add them here, i will precommit.
I think, you want to operate on `<4 x i32>`, with the run line

  ; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=+sse2 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SSE2

and

  ; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s

Just completely duplicate the existing test files with `-vector` suffix. I.e. if you have

  define i32 @test_urem_odd(i32 %X) nounwind readnone {
    %urem = urem i32 %X, 5
    %cmp = icmp eq i32 %urem, 0
    %ret = zext i1 %cmp to i32
    ret i32 %ret
  }

It will be

  define <4 x i32> @test_urem_odd_vec(<4 x i32> %X) nounwind readnone {
    %urem = urem <4 x i32> %X, <i32 5, i32 5, i32 5, i32 5>
    %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
    %ret = zext <4 x i1> %cmp to <4 x i32>
    ret <4 x i32> %ret
  }

I'm not quite sure about nonsplat tests. things to keep in mind there:

- You have two constants, so add three positive tests with one constant element being `undef` (i.e. first test with undef in the first constant, second test with undef in the second constant, and a test with undef in both)
- The codepath is different depending on whether the divisor is even. So you want to add a test where half of the divisor is even, and half is odd
- ???


Repository:
  rL LLVM

https://reviews.llvm.org/D50222