[llvm] r341605 - [X86] Add a test case showing failure to use the RMW form of ADC when the load is in operand 1 going into isel.

[Craig Topper via llvm-commits]

Author: ctopper
Date: Thu Sep  6 16:55:34 2018
New Revision: 341605

URL: http://llvm.org/viewvc/llvm-project?rev=341605&view=rev
Log:
[X86] Add a test case showing failure to use the RMW form of ADC when the load is in operand 1 going into isel.

The ADC instruction is commutable, but we only have RMW isel patterns with a load on the left hand side. Nothing will canonicalize loads to the LHS on these ops. So we need two patterns.

Modified:
    llvm/trunk/test/CodeGen/X86/addcarry.ll

Modified: llvm/trunk/test/CodeGen/X86/addcarry.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/addcarry.ll?rev=341605&r1=341604&r2=341605&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/addcarry.ll (original)
+++ llvm/trunk/test/CodeGen/X86/addcarry.ll Thu Sep  6 16:55:34 2018
@@ -14,6 +14,34 @@ entry:
   ret i128 %0
 }
 
+define void @add128_rmw(i128* %a, i128 %b) nounwind {
+; CHECK-LABEL: add128_rmw:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addq %rsi, (%rdi)
+; CHECK-NEXT:    adcq %rdx, 8(%rdi)
+; CHECK-NEXT:    retq
+entry:
+  %0 = load i128, i128* %a
+  %1 = add i128 %0, %b
+  store i128 %1, i128* %a
+  ret void
+}
+
+define void @add128_rmw2(i128 %a, i128* %b) nounwind {
+; CHECK-LABEL: add128_rmw2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addq (%rdx), %rdi
+; CHECK-NEXT:    adcq 8(%rdx), %rsi
+; CHECK-NEXT:    movq %rdi, (%rdx)
+; CHECK-NEXT:    movq %rsi, 8(%rdx)
+; CHECK-NEXT:    retq
+entry:
+  %0 = load i128, i128* %b
+  %1 = add i128 %a, %0
+  store i128 %1, i128* %b
+  ret void
+}
+
 define i256 @add256(i256 %a, i256 %b) nounwind {
 ; CHECK-LABEL: add256:
 ; CHECK:       # %bb.0: # %entry