[llvm] r341596 - [X86] Add isel patterns for commuting X86adc_flag with a load in the LHS.

[Craig Topper via llvm-commits]

Author: ctopper
Date: Thu Sep  6 15:41:44 2018
New Revision: 341596

URL: http://llvm.org/viewvc/llvm-project?rev=341596&view=rev
Log:
[X86] Add isel patterns for commuting X86adc_flag with a load in the LHS.

The peephole pass likely gets this normally, but we should be doing it during isel.

Ideally we'd just make the X86adc_flag pattern SDNPCommutable, but the tablegen doesn't handle that when one of the operands is a register reference.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
    llvm/trunk/lib/Target/X86/X86InstrArithmetic.td

Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=341596&r1=341595&r2=341596&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Thu Sep  6 15:41:44 2018
@@ -522,7 +522,9 @@ X86DAGToDAGISel::IsProfitableToFold(SDVa
     switch (U->getOpcode()) {
     default: break;
     case X86ISD::ADD:
+    case X86ISD::ADC:
     case X86ISD::SUB:
+    case X86ISD::SBB:
     case X86ISD::AND:
     case X86ISD::XOR:
     case X86ISD::OR:

Modified: llvm/trunk/lib/Target/X86/X86InstrArithmetic.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrArithmetic.td?rev=341596&r1=341595&r2=341596&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrArithmetic.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrArithmetic.td Thu Sep  6 15:41:44 2018
@@ -1176,6 +1176,16 @@ let isCompare = 1 in {
 defm CMP : ArithBinOp_F<0x38, 0x3A, 0x3C, "cmp", MRM7r, MRM7m, X86cmp, 0, 0>;
 }
 
+// Patterns to recognize loads on the LHS of an ADC. We can't make X86adc_flag
+// commutable since it has EFLAGs as an input.
+def : Pat<(X86adc_flag (loadi8 addr:$src1), GR8:$src2, EFLAGS),
+          (ADC8rm GR8:$src2, addr:$src1)>;
+def : Pat<(X86adc_flag (loadi16 addr:$src1), GR16:$src2, EFLAGS),
+          (ADC16rm GR16:$src2, addr:$src1)>;
+def : Pat<(X86adc_flag (loadi32 addr:$src1), GR32:$src2, EFLAGS),
+          (ADC32rm GR32:$src2, addr:$src1)>;
+def : Pat<(X86adc_flag (loadi64 addr:$src1), GR64:$src2, EFLAGS),
+          (ADC64rm GR64:$src2, addr:$src1)>;
 
 //===----------------------------------------------------------------------===//
 // Semantically, test instructions are similar like AND, except they don't