[PATCH] D51737: DAG: Combine extract_vector_elt of concat_vectors

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: RKSimon, hliao.
Herald added subscribers: nhaehnle, wdng, jvesely.

Fixes extra canonicalize regressions when legalizing
vector fminnum/fmaxnum.


https://reviews.llvm.org/D51737

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/AMDGPU/reduction.ll


Index: test/CodeGen/AMDGPU/reduction.ll
===================================================================
--- test/CodeGen/AMDGPU/reduction.ll
+++ test/CodeGen/AMDGPU/reduction.ll
@@ -438,10 +438,8 @@
 ; GFX9-NEXT: v_pk_max_f16 [[CANON1:v[0-9]+]], v1, v1
 ; GFX9-NEXT: v_pk_max_f16 [[CANON0:v[0-9]+]], v0, v0
 ; GFX9-NEXT: v_pk_max_f16 [[MAX:v[0-9]+]], [[CANON0]], [[CANON1]]{{$}}
+; GFX9-NEXT: v_max_f16_sdwa v{{[0-9]+}}, [[MAX]], [[MAX]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
 
-; FIXME: Extra canonicalize leftover
-; GFX9-NEXT: v_max_f16_sdwa [[TMP:v[0-9]+]], [[MAX]], [[MAX]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-NEXT: v_max_f16_e32 v0, [[MAX]], [[TMP]]
 
 ; VI-DAG: v_max_f16_sdwa [[CANON1:v[0-9]+]], v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
 ; VI-DAG: v_max_f16_sdwa [[CANON3:v[0-9]+]], v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
@@ -466,11 +464,7 @@
 ; GFX9-NEXT: v_pk_max_f16 [[CANON1:v[0-9]+]], v1, v1
 ; GFX9-NEXT: v_pk_max_f16 [[CANON0:v[0-9]+]], v0, v0
 ; GFX9-NEXT: v_pk_min_f16 [[MIN:v[0-9]+]], [[CANON0]], [[CANON1]]{{$}}
-
-; FIXME: Extra canonicalize leftover
-; GFX9-NEXT: v_max_f16_sdwa [[TMP:v[0-9]+]], [[MIN]], [[MIN]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-NEXT: v_min_f16_e32 v0, [[MIN]], [[TMP]]
-
+; GFX9-NEXT: v_min_f16_sdwa v{{[0-9]+}}, [[MIN]], [[MIN]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
 
 ; VI-DAG: v_max_f16_sdwa [[CANON1:v[0-9]+]], v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
 ; VI-DAG: v_max_f16_sdwa [[CANON3:v[0-9]+]], v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
Index: lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -15489,6 +15489,27 @@
         Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems;
         EltNo = DAG.getConstant(Elt, SDLoc(EltNo), EltNo.getValueType());
       }
+    } else if (InVec.getOpcode() == ISD::CONCAT_VECTORS &&
+               !BCNumEltsChanged) {
+      // extract_vector_elt (concat_vectors v2i16:a, v2i16:b), 0
+      //      -> extract_vector_elt a, 0
+      // extract_vector_elt (concat_vectors v2i16:a, v2i16:b), 1
+      //      -> extract_vector_elt a, 1
+      // extract_vector_elt (concat_vectors v2i16:a, v2i16:b), 2
+      //      -> extract_vector_elt b, 0
+      // extract_vector_elt (concat_vectors v2i16:a, v2i16:b), 3
+      //      -> extract_vector_elt b, 1
+      SDLoc SL(N);
+      EVT ConcatVT = InVec.getOperand(0).getValueType();
+      unsigned ConcatNumElts = ConcatVT.getVectorNumElements();
+      SDValue NewIdx = DAG.getConstant(Elt % ConcatNumElts, SL,
+                                       EltNo.getValueType());
+
+      SDValue ConcatOp = InVec.getOperand(Elt / ConcatNumElts);
+      SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL,
+                                ConcatVT.getVectorElementType(),
+                                ConcatOp, NewIdx);
+      return DAG.getNode(ISD::BITCAST, SL, NVT, Elt);
     }
 
     // Make sure we found a non-volatile load and the extractelement is


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