[PATCH] D50572: DAG: Handle odd vector sizes in calling conv splitting

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: lib/Target/AMDGPU/SIISelLowering.cpp:742
 
     // FIXME: Fails to break down as we want with v3.
+    if (Size == 16 && Subtarget->has16BitInsts())
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Update the FIXME comment?


https://reviews.llvm.org/D50572