[PATCH] D51696: [SelectionDAG] enhance vector demanded elements to look at a vector select condition operand

[Sanjay Patel via Phabricator via llvm-commits]

spatel added inline comments.


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Comment at: lib/CodeGen/SelectionDAG/TargetLowering.cpp:1539
+    // TODO - add support for constant vselect masks (see IR version of this).
+    APInt UnusedUndef, UnusedZero;
+    if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedElts, UnusedUndef,
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RKSimon wrote:
> Can we use UnusedZero to alter the LHS/RHS DemandedElts ?
If UnusedZero (if we do use it, I'll change the name of course) has set bits, that would mean that we're choosing RHS elements in this select, right?

UnusedUndef is probably the more interesting part, and that's what the TODO comment is alluding to. I'm not sure what we decided on this: if an element of the condition is undef, does that mean the result is undef? In that case, I think we could do something like this below here:
KnownUndef = UndefCond | (UndefLHS & UndefRHS);

I did try that change, but there were no existing test diffs, so I thought it was better left for a follow-up.


https://reviews.llvm.org/D51696