[PATCH] D51696: [SelectionDAG] enhance vector demanded elements to look at a vector select condition operand
Sanjay Patel via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 5 11:23:55 PDT 2018
spatel created this revision.
spatel added reviewers: craig.topper, RKSimon, efriedma.
Herald added a subscriber: mcrosier.
This is the DAG equivalent of https://reviews.llvm.org/D51433.
If we know we're not using all vector lanes, use that knowledge to potentially simplify a vselect condition.
The reduction/horizontal tests show that we are eliminating AVX1 operations on the upper half of 256-bit vectors because we don't need those anyway (double-check to make sure I'm reading those diffs correctly).
I'm not sure what the pr34592 test is showing. That's run with -O0; is SimplifyDemandedVectorElts supposed to be running there?
The removal of the temporary DemandedLHS/DemandedRHS variables is NFC, so we could make that a pre-commit IIUC.
https://reviews.llvm.org/D51696
Files:
lib/CodeGen/SelectionDAG/TargetLowering.cpp
test/CodeGen/X86/horizontal-reduce-smax.ll
test/CodeGen/X86/horizontal-reduce-smin.ll
test/CodeGen/X86/horizontal-reduce-umax.ll
test/CodeGen/X86/horizontal-reduce-umin.ll
test/CodeGen/X86/pr34592.ll
test/CodeGen/X86/vector-reduce-smax.ll
test/CodeGen/X86/vector-reduce-smin.ll
test/CodeGen/X86/vector-reduce-umax.ll
test/CodeGen/X86/vector-reduce-umin.ll
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