[llvm] r341331 - Revert [Hexagon] Add support for getRegisterByName.

[Sid Manning via llvm-commits]

Author: sidneym
Date: Mon Sep  3 10:59:10 2018
New Revision: 341331

URL: http://llvm.org/viewvc/llvm-project?rev=341331&view=rev
Log:
Revert [Hexagon] Add support for getRegisterByName.

Support required to build the Hexagon Linux kernel.

Removed:
    llvm/trunk/test/CodeGen/Hexagon/namedreg.ll
Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
    llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h

Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp?rev=341331&r1=341330&r2=341331&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp Mon Sep  3 10:59:10 2018
@@ -22,7 +22,6 @@
 #include "llvm/ADT/APInt.h"
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/SmallVector.h"
-#include "llvm/ADT/StringSwitch.h"
 #include "llvm/CodeGen/CallingConvLower.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
@@ -241,51 +240,6 @@ bool HexagonTargetLowering::mayBeEmitted
   return true;
 }
 
-unsigned  HexagonTargetLowering::getRegisterByName(const char* RegName, EVT VT,
-                                              SelectionDAG &DAG) const {
-  unsigned Reg = StringSwitch<unsigned>(RegName)
-                     .Case("r0", Hexagon::R0)
-                     .Case("r1", Hexagon::R1)
-                     .Case("r2", Hexagon::R2)
-                     .Case("r3", Hexagon::R3)
-                     .Case("r4", Hexagon::R4)
-                     .Case("r5", Hexagon::R5)
-                     .Case("r6", Hexagon::R6)
-                     .Case("r7", Hexagon::R7)
-                     .Case("r8", Hexagon::R8)
-                     .Case("r9", Hexagon::R9)
-                     .Case("r10", Hexagon::R10)
-                     .Case("r11", Hexagon::R11)
-                     .Case("r12", Hexagon::R12)
-                     .Case("r13", Hexagon::R13)
-                     .Case("r14", Hexagon::R14)
-                     .Case("r15", Hexagon::R15)
-                     .Case("r16", Hexagon::R16)
-                     .Case("r17", Hexagon::R17)
-                     .Case("r18", Hexagon::R18)
-                     .Case("r19", Hexagon::R19)
-                     .Case("r20", Hexagon::R20)
-                     .Case("r21", Hexagon::R21)
-                     .Case("r22", Hexagon::R22)
-                     .Case("r23", Hexagon::R23)
-                     .Case("r24", Hexagon::R24)
-                     .Case("r25", Hexagon::R25)
-                     .Case("r26", Hexagon::R26)
-                     .Case("r27", Hexagon::R27)
-                     .Case("r28", Hexagon::R28)
-                     .Case("r29", Hexagon::R29)
-                     .Case("sp", Hexagon::R29)
-                     .Case("r30", Hexagon::R30)
-                     .Case("fp", Hexagon::R30)
-                     .Case("r31", Hexagon::R31)
-                     .Case("sp", Hexagon::R31)
-                     .Default(0);
-  if (Reg)
-    return Reg;
-
-  report_fatal_error("Invalid register name global variable");
-}
-
 /// LowerCallResult - Lower the result values of an ISD::CALL into the
 /// appropriate copies out of appropriate physical registers.  This assumes that
 /// Chain/Glue are the input chain/glue to use, and that TheCall is the call

Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h?rev=341331&r1=341330&r2=341331&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h Mon Sep  3 10:59:10 2018
@@ -223,9 +223,6 @@ namespace HexagonISD {
 
     bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
 
-    unsigned getRegisterByName(const char* RegName, EVT VT,
-                               SelectionDAG &DAG) const override;
-
     /// If a physical register, this returns the register that receives the
     /// exception address on entry to an EH pad.
     unsigned

Removed: llvm/trunk/test/CodeGen/Hexagon/namedreg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/namedreg.ll?rev=341330&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/namedreg.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/namedreg.ll (removed)
@@ -1,23 +0,0 @@
-; RUN: llc -march=hexagon < %s | FileCheck %s
-define dso_local i32 @r19f() #0 {
-entry:
-  %0 = call i32 @llvm.read_register.i32(metadata !0)
-  ret i32 %0
-}
-
-; Function Attrs: noinline nounwind optnone
-define dso_local i32 @spf() #0 {
-entry:
-  %0 = call i32 @llvm.read_register.i32(metadata !1)
-  ret i32 %0
-}
-
-declare i32 @llvm.read_register.i32(metadata) #1
-
-!llvm.named.register.r19 = !{!0}
-!llvm.named.register.sp = !{!1}
-
-!0 = !{!"r19"}
-!1 = !{!"sp"}
-; CHECK: r0 = r19
-; CHECK: r0 = r29