[llvm] r341277 - [AVR] Redefine the 'SBR' instruction as an alias

[Dylan McKay via llvm-commits]

Author: dylanmckay
Date: Sat Sep  1 05:22:54 2018
New Revision: 341277

URL: http://llvm.org/viewvc/llvm-project?rev=341277&view=rev
Log:
[AVR] Redefine the 'SBR' instruction as an alias

This fixes a TableGen warning about duplicate bit patterns.

SBR
===

This is an alias of 'ORI Rd, K'.

Modified:
    llvm/trunk/lib/Target/AVR/AVRInstrInfo.td
    llvm/trunk/test/MC/AVR/inst-sbr.s

Modified: llvm/trunk/lib/Target/AVR/AVRInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AVR/AVRInstrInfo.td?rev=341277&r1=341276&r2=341277&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AVR/AVRInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AVR/AVRInstrInfo.td Sat Sep  1 05:22:54 2018
@@ -732,6 +732,14 @@ Defs = [SREG] in
 // This operation is identical to a `Rd AND Rd`.
 def : InstAlias<"tst\t$rd", (ANDRdRr GPR8:$rd, GPR8:$rd)>;
 
+// SBR Rd, K
+//
+// Mnemonic alias to 'ORI Rd, K'. Same bit pattern, same operands,
+// same everything.
+def : InstAlias<"sbr\t$rd, $k",
+                (ORIRdK LD8:$rd, imm_ldi8:$k),
+                /* Disable display, so we don't override ORI */ 0>;
+
 //===----------------------------------------------------------------------===//
 // Jump instructions
 //===----------------------------------------------------------------------===//
@@ -1730,15 +1738,6 @@ def BLD : FRdB<0b00,
 let Constraints = "$src = $rd",
 Defs = [SREG] in
 {
-  // SBR Rd, K
-  // Alias for ORI Rd, K
-  def SBRRdK : FRdK<0b0110,
-                    (outs LD8:$rd),
-                    (ins LD8:$src, imm_ldi8:$k),
-                    "sbr\t$rd, $k",
-                    [(set i8:$rd, (or i8:$src, imm:$k)),
-                     (implicit SREG)]>;
-
   // CBR Rd, K
   // Alias for `ANDI Rd, COM(K)` where COM(K) is the complement of K.
   // FIXME: This uses the 'complement' encoder. We need it to also use the

Modified: llvm/trunk/test/MC/AVR/inst-sbr.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AVR/inst-sbr.s?rev=341277&r1=341276&r2=341277&view=diff
==============================================================================
--- llvm/trunk/test/MC/AVR/inst-sbr.s (original)
+++ llvm/trunk/test/MC/AVR/inst-sbr.s Sat Sep  1 05:22:54 2018
@@ -9,10 +9,10 @@ foo:
 
   sbr r19, _start
 
-; CHECK: sbr r17, 208                  ; encoding: [0x10,0x6d]
-; CHECK: sbr r24, 190                  ; encoding: [0x8e,0x6b]
-; CHECK: sbr r20, 173                  ; encoding: [0x4d,0x6a]
-; CHECK: sbr r31, 0                    ; encoding: [0xf0,0x60]
+; CHECK: ori r17, 208                  ; encoding: [0x10,0x6d]
+; CHECK: ori r24, 190                  ; encoding: [0x8e,0x6b]
+; CHECK: ori r20, 173                  ; encoding: [0x4d,0x6a]
+; CHECK: ori r31, 0                    ; encoding: [0xf0,0x60]
 
-; CHECK: sbr     r19, _start           ; encoding: [0x30'A',0x60]
+; CHECK: ori     r19, _start           ; encoding: [0x30'A',0x60]
 ; CHECK:                               ;   fixup A - offset: 0, value: _start, kind: fixup_ldi