[PATCH] D51570: [X86][XOP] VFRCZ* instructions should be in their own sched class

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri created this revision.
lebedev.ri added reviewers: RKSimon, craig.topper, avt77, andreadb, spatel.
Herald added a subscriber: courbet.

VFRCZ* are AMD XOP instructions.
That instruction set is only supported by `bdver[1-4]` cpu models.

These instructions are unrelated to the instructions grouped by the `WriteFRnd` sched class.
On `bdver[1-3]`, they have latency of `10`, as per agner's tables,
and as per my llvm-exegesis measurements for `bdver2`.
Which is different from what `WriteFRnd` specifies (`5`).

Now, the test coverage is saddening. We //currently// don't have any
dedicated sched models for any of these 4 cpu's, so the test coverage decreases.
I'm not sure this can be improved, until the said sched model is ready for integration...


Repository:
  rL LLVM

https://reviews.llvm.org/D51570

Files:
  lib/Target/X86/X86InstrXOP.td
  lib/Target/X86/X86SchedBroadwell.td
  lib/Target/X86/X86SchedHaswell.td
  lib/Target/X86/X86SchedSandyBridge.td
  lib/Target/X86/X86SchedSkylakeClient.td
  lib/Target/X86/X86SchedSkylakeServer.td
  lib/Target/X86/X86Schedule.td
  lib/Target/X86/X86ScheduleAtom.td
  lib/Target/X86/X86ScheduleBtVer2.td
  lib/Target/X86/X86ScheduleSLM.td
  lib/Target/X86/X86ScheduleZnver1.td
  test/CodeGen/X86/xop-schedule.ll
  test/tools/llvm-mca/X86/Generic/resources-xop.s
  test/tools/llvm-mca/X86/Generic/xop-super-registers-1.s

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