[PATCH] D51502: [X86] Fix register resizings for inline assembly register operands.

[Nick Desaulniers via Phabricator via llvm-commits]

nickdesaulniers added inline comments.


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Comment at: llvm/test/CodeGen/X86/pr38730.ll:22
+  %0 = load i32, i32* @a, align 4
+  %1 = tail call { i64, i32 } asm "", "={edx},=r,1,~{dirflag},~{fpsr},~{flags}"(i32 %0)
+  %asmresult1 = extractvalue { i64, i32 } %1, 1
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srhines wrote:
> efriedma wrote:
> > Shouldn't this be an error? I can't see how it's possible to put a 64-bit value into edx.
> GCC issues a warning for this, but then uses two registers (one being the specified edx).
See also: https://lore.kernel.org/patchwork/patch/403136/


Repository:
  rL LLVM

https://reviews.llvm.org/D51502