[PATCH] D50790: [RISCV] Fixed SmallVector.h Assertion `idx < size()'

[Ana Pazos via Phabricator via llvm-commits]

apazos updated this revision to Diff 163361.
apazos retitled this revision from " [RISCV] Fixed SmallVector.h Assertion `idx < size()' failed" to " [RISCV] Fixed SmallVector.h Assertion `idx < size()'".
apazos edited the summary of this revision.
apazos added a subscriber: llvm-commits.
apazos added a comment.

Added a FIXME comment about jal behavior that needs fixing.


https://reviews.llvm.org/D50790

Files:
  lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  test/MC/RISCV/rv32i-invalid.s


Index: test/MC/RISCV/rv32i-invalid.s
===================================================================
--- test/MC/RISCV/rv32i-invalid.s
+++ test/MC/RISCV/rv32i-invalid.s
@@ -138,6 +138,8 @@
 # Too few operands
 ori a0, a1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 xor s2, s2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# FIXME: Fix jal behavior to interpret a3 as a symbol rathen than a register.
+jal a3     # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 
 # Instruction not in the base ISA
 mul a4, ra, s0 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled
Index: lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===================================================================
--- lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -684,7 +684,9 @@
                                              bool MatchingInlineAsm) {
   MCInst Inst;
 
-  switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
+  auto Result =
+    MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);
+  switch (Result) {
   default:
     break;
   case Match_Success:
@@ -705,6 +707,20 @@
     }
     return Error(ErrorLoc, "invalid operand for instruction");
   }
+  }
+
+  // Handle the case when the error message is of specific type
+  // other than the generic Match_InvalidOperand, and the
+  // corresponding // operand is missing.
+  if (Result > FIRST_TARGET_MATCH_RESULT_TY) {
+    SMLoc ErrorLoc = IDLoc;
+    if (ErrorInfo != ~0U && ErrorInfo >= Operands.size())
+        return Error(ErrorLoc, "too few operands for instruction");
+  }
+
+  switch(Result) {
+  default:
+    break;
   case Match_InvalidImmXLen:
     if (isRV64()) {
       SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();


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