[llvm] r341024 - [X86] Improved sched model for X86 CMPXCHG* instructions.
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 30 09:17:44 PDT 2018
Please include more context in your submission messages. *How* did you
improve scheduling? What is the visible impact?
On 08/29/2018 11:26 PM, Andrew V. Tischenko via llvm-commits wrote:
> Author: avt77
> Date: Wed Aug 29 23:26:00 2018
> New Revision: 341024
>
> URL: http://llvm.org/viewvc/llvm-project?rev=341024&view=rev
> Log:
> [X86] Improved sched model for X86 CMPXCHG* instructions.
> Differential Revision: https://reviews.llvm.org/D50070
>
> Modified:
> llvm/trunk/lib/Target/X86/X86InstrInfo.td
> llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
> llvm/trunk/lib/Target/X86/X86SchedHaswell.td
> llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
> llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
> llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
> llvm/trunk/lib/Target/X86/X86Schedule.td
> llvm/trunk/lib/Target/X86/X86ScheduleAtom.td
> llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
> llvm/trunk/lib/Target/X86/X86ScheduleSLM.td
> llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
> llvm/trunk/test/CodeGen/X86/schedule-x86_64.ll
> llvm/trunk/test/tools/llvm-mca/X86/Generic/resources-x86_64.s
> llvm/trunk/test/tools/llvm-mca/X86/SandyBridge/resources-x86_64.s
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=341024&r1=341023&r2=341024&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Wed Aug 29 23:26:00 2018
> @@ -2061,7 +2061,7 @@ def XADD64rm : RI<0xC1, MRMSrcMem, (out
>
> }
>
> -let SchedRW = [WriteALU], hasSideEffects = 0 in {
> +let SchedRW = [WriteCMPXCHG], hasSideEffects = 0 in {
> let Defs = [AL, EFLAGS], Uses = [AL] in
> def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
> "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB,
> @@ -2080,7 +2080,7 @@ def CMPXCHG64rr : RI<0xB1, MRMDestReg,
> NotMemoryFoldable;
> } // SchedRW, hasSideEffects
>
> -let SchedRW = [WriteALULd, WriteRMW], mayLoad = 1, mayStore = 1,
> +let SchedRW = [WriteCMPXCHGRMW], mayLoad = 1, mayStore = 1,
> hasSideEffects = 0 in {
> let Defs = [AL, EFLAGS], Uses = [AL] in
> def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
>
> Modified: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=341024&r1=341023&r2=341024&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (original)
> +++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td Wed Aug 29 23:26:00 2018
> @@ -119,6 +119,8 @@ defm : BWWriteResPair<WriteIDiv16, [BWPo
> defm : BWWriteResPair<WriteIDiv32, [BWPort0, BWDivider], 25, [1, 10]>;
> defm : BWWriteResPair<WriteIDiv64, [BWPort0, BWDivider], 25, [1, 10]>;
>
> +defm : X86WriteRes<WriteCMPXCHG,[BWPort06, BWPort0156], 5, [2, 3], 5>;
> +defm : X86WriteRes<WriteCMPXCHGRMW,[BWPort23, BWPort06, BWPort0156, BWPort237, BWPort4], 8, [1, 2, 1, 1, 1], 6>;
> defm : X86WriteRes<WriteBSWAP32, [BWPort15], 1, [1], 1>;
> defm : X86WriteRes<WriteBSWAP64, [BWPort06, BWPort15], 2, [1, 1], 2>;
> defm : X86WriteRes<WriteXCHG, [BWPort0156], 2, [3], 3>;
> @@ -939,13 +941,6 @@ def BWWriteResGroup55 : SchedWriteRes<[B
> }
> def: InstRW<[BWWriteResGroup55], (instrs XSETBV)>;
>
> -def BWWriteResGroup56 : SchedWriteRes<[BWPort06,BWPort0156]> {
> - let Latency = 5;
> - let NumMicroOps = 5;
> - let ResourceCycles = [2,3];
> -}
> -def: InstRW<[BWWriteResGroup56], (instregex "CMPXCHG(8|16|32|64)rr")>;
> -
> def BWWriteResGroup57 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> {
> let Latency = 5;
> let NumMicroOps = 6;
> @@ -1214,8 +1209,7 @@ def BWWriteResGroup100 : SchedWriteRes<[
> let ResourceCycles = [1,1,1,2,1];
> }
> def : SchedAlias<WriteADCRMW, BWWriteResGroup100>;
> -def: InstRW<[BWWriteResGroup100], (instregex "CMPXCHG(8|16|32|64)rm",
> - "ROL(8|16|32|64)mCL",
> +def: InstRW<[BWWriteResGroup100], (instregex "ROL(8|16|32|64)mCL",
> "SAR(8|16|32|64)mCL",
> "SHL(8|16|32|64)mCL",
> "SHR(8|16|32|64)mCL")>;
>
> Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=341024&r1=341023&r2=341024&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
> +++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Wed Aug 29 23:26:00 2018
> @@ -126,6 +126,8 @@ defm : HWWriteResPair<WriteIMul64, [HWPo
>
> defm : X86WriteRes<WriteBSWAP32, [HWPort15], 1, [1], 1>;
> defm : X86WriteRes<WriteBSWAP64, [HWPort06, HWPort15], 2, [1,1], 2>;
> +defm : X86WriteRes<WriteCMPXCHG,[HWPort06, HWPort0156], 5, [2,3], 5>;
> +defm : X86WriteRes<WriteCMPXCHGRMW,[HWPort23,HWPort06,HWPort0156,HWPort237,HWPort4], 9, [1,2,1,1,1], 6>;
> defm : X86WriteRes<WriteXCHG, [HWPort0156], 2, [3], 3>;
>
> def : WriteRes<WriteIMulH, []> { let Latency = 3; }
> @@ -1349,8 +1351,7 @@ def HWWriteResGroup69 : SchedWriteRes<[H
> let NumMicroOps = 6;
> let ResourceCycles = [1,1,1,2,1];
> }
> -def: InstRW<[HWWriteResGroup69], (instregex "CMPXCHG(8|16|32|64)rm",
> - "ROL(8|16|32|64)mCL",
> +def: InstRW<[HWWriteResGroup69], (instregex "ROL(8|16|32|64)mCL",
> "SAR(8|16|32|64)mCL",
> "SHL(8|16|32|64)mCL",
> "SHR(8|16|32|64)mCL")>;
> @@ -1578,13 +1579,6 @@ def HWWriteResGroup100 : SchedWriteRes<[
> }
> def: InstRW<[HWWriteResGroup100], (instrs XSETBV)>;
>
> -def HWWriteResGroup101 : SchedWriteRes<[HWPort06,HWPort0156]> {
> - let Latency = 5;
> - let NumMicroOps = 5;
> - let ResourceCycles = [2,3];
> -}
> -def: InstRW<[HWWriteResGroup101], (instregex "CMPXCHG(8|16|32|64)rr")>;
> -
> def HWWriteResGroup102 : SchedWriteRes<[HWPort1,HWPort5]> {
> let Latency = 6;
> let NumMicroOps = 2;
>
> Modified: llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td?rev=341024&r1=341023&r2=341024&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td (original)
> +++ llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td Wed Aug 29 23:26:00 2018
> @@ -114,7 +114,9 @@ defm : SBWriteResPair<WriteIMul64, [SBPo
> defm : X86WriteRes<WriteXCHG, [SBPort015], 2, [3], 3>;
>
> defm : X86WriteRes<WriteBSWAP32, [SBPort1], 1, [1], 1>;
> -defm : X86WriteRes<WriteBSWAP64, [SBPort1,SBPort05], 2, [1,1], 2>;
> +defm : X86WriteRes<WriteBSWAP64, [SBPort1, SBPort05], 2, [1,1], 2>;
> +defm : X86WriteRes<WriteCMPXCHG, [SBPort05, SBPort015], 5, [1,3], 4>;
> +defm : X86WriteRes<WriteCMPXCHGRMW,[SBPort015, SBPort5, SBPort23, SBPort4], 8, [1, 2, 2, 1], 6>;
>
> defm : SBWriteResPair<WriteDiv8, [SBPort0, SBDivider], 25, [1, 10]>;
> defm : SBWriteResPair<WriteDiv16, [SBPort0, SBDivider], 25, [1, 10]>;
> @@ -770,13 +772,6 @@ def SBWriteResGroup41 : SchedWriteRes<[S
> }
> def: InstRW<[SBWriteResGroup41], (instrs FNINIT)>;
>
> -def SBWriteResGroup42 : SchedWriteRes<[SBPort05,SBPort015]> {
> - let Latency = 5;
> - let NumMicroOps = 4;
> - let ResourceCycles = [1,3];
> -}
> -def: InstRW<[SBWriteResGroup42], (instregex "CMPXCHG(8|16|32|64)rr")>;
> -
> def SBWriteResGroup43 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> {
> let Latency = 3;
> let NumMicroOps = 4;
> @@ -953,12 +948,12 @@ def SBWriteResGroup77 : SchedWriteRes<[S
> }
> def: InstRW<[SBWriteResGroup77], (instregex "(V?)(U?)COMI(SD|SS)rm")>;
>
> -def SBWriteResGroup81 : SchedWriteRes<[SBPort23,SBPort015]> {
> - let Latency = 8;
> - let NumMicroOps = 4;
> - let ResourceCycles = [1,3];
> +def SBWriteResGroup81 : SchedWriteRes<[SBPort4, SBPort23, SBPort015]> {
> + let Latency = 6;
> + let NumMicroOps = 3;
> + let ResourceCycles = [1, 2, 1];
> }
> -def: InstRW<[SBWriteResGroup81], (instregex "CMPXCHG(8|16|32|64)rm")>;
> +def: InstRW<[SBWriteResGroup81], (instregex "CMPXCHG(8|16)B")>;
>
> def SBWriteResGroup83 : SchedWriteRes<[SBPort23,SBPort015]> {
> let Latency = 8;
>
> Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=341024&r1=341023&r2=341024&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
> +++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Wed Aug 29 23:26:00 2018
> @@ -112,6 +112,8 @@ defm : SKLWriteResPair<WriteIMul64, [SKL
>
> defm : X86WriteRes<WriteBSWAP32, [SKLPort15], 1, [1], 1>;
> defm : X86WriteRes<WriteBSWAP64, [SKLPort06, SKLPort15], 2, [1,1], 2>;
> +defm : X86WriteRes<WriteCMPXCHG,[SKLPort06, SKLPort0156], 5, [2,3], 5>;
> +defm : X86WriteRes<WriteCMPXCHGRMW,[SKLPort23,SKLPort06,SKLPort0156,SKLPort237,SKLPort4], 8, [1,2,1,1,1], 6>;
> defm : X86WriteRes<WriteXCHG, [SKLPort0156], 2, [3], 3>;
>
> defm : SKLWriteResPair<WriteDiv8, [SKLPort0, SKLDivider], 25, [1,10], 1, 4>;
> @@ -965,13 +967,6 @@ def SKLWriteResGroup63 : SchedWriteRes<[
> }
> def: InstRW<[SKLWriteResGroup63], (instrs XSETBV)>;
>
> -def SKLWriteResGroup64 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
> - let Latency = 5;
> - let NumMicroOps = 5;
> - let ResourceCycles = [2,3];
> -}
> -def: InstRW<[SKLWriteResGroup64], (instregex "CMPXCHG(8|16|32|64)rr")>;
> -
> def SKLWriteResGroup65 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> {
> let Latency = 5;
> let NumMicroOps = 6;
> @@ -1311,7 +1306,6 @@ def SKLWriteResGroup119 : SchedWriteRes<
> let ResourceCycles = [1,1,1,2,1];
> }
> def: SchedAlias<WriteADCRMW, SKLWriteResGroup119>;
> -def: InstRW<[SKLWriteResGroup119], (instregex "CMPXCHG(8|16|32|64)rm")>;
>
> def SKLWriteResGroup120 : SchedWriteRes<[SKLPort0,SKLPort23]> {
> let Latency = 9;
>
> Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=341024&r1=341023&r2=341024&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
> +++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Wed Aug 29 23:26:00 2018
> @@ -112,6 +112,8 @@ defm : SKXWriteResPair<WriteIMul64, [SKX
>
> defm : X86WriteRes<WriteBSWAP32, [SKXPort15], 1, [1], 1>;
> defm : X86WriteRes<WriteBSWAP64, [SKXPort06, SKXPort15], 2, [1,1], 2>;
> +defm : X86WriteRes<WriteCMPXCHG,[SKXPort06, SKXPort0156], 5, [2,3], 5>;
> +defm : X86WriteRes<WriteCMPXCHGRMW,[SKXPort23,SKXPort06,SKXPort0156,SKXPort237,SKXPort4], 8, [1,2,1,1,1], 6>;
> defm : X86WriteRes<WriteXCHG, [SKXPort0156], 2, [3], 3>;
>
> defm : SKXWriteResPair<WriteDiv8, [SKXPort0, SKXDivider], 25, [1,10], 1, 4>;
> @@ -1126,13 +1128,6 @@ def SKXWriteResGroup67 : SchedWriteRes<[
> }
> def: InstRW<[SKXWriteResGroup67], (instrs XSETBV)>;
>
> -def SKXWriteResGroup68 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
> - let Latency = 5;
> - let NumMicroOps = 5;
> - let ResourceCycles = [2,3];
> -}
> -def: InstRW<[SKXWriteResGroup68], (instregex "CMPXCHG(8|16|32|64)rr")>;
> -
> def SKXWriteResGroup69 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort0156]> {
> let Latency = 5;
> let NumMicroOps = 6;
> @@ -1664,7 +1659,6 @@ def SKXWriteResGroup130 : SchedWriteRes<
> let ResourceCycles = [1,1,1,2,1];
> }
> def: SchedAlias<WriteADCRMW, SKXWriteResGroup130>;
> -def: InstRW<[SKXWriteResGroup130], (instregex "CMPXCHG(8|16|32|64)rm")>;
>
> def SKXWriteResGroup131 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
> let Latency = 8;
>
> Modified: llvm/trunk/lib/Target/X86/X86Schedule.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Schedule.td?rev=341024&r1=341023&r2=341024&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86Schedule.td (original)
> +++ llvm/trunk/lib/Target/X86/X86Schedule.td Wed Aug 29 23:26:00 2018
> @@ -120,7 +120,9 @@ def WriteLEA : SchedWrite; //
>
> def WriteBSWAP32 : SchedWrite; // Byte Order (Endianness) 32-bit Swap.
> def WriteBSWAP64 : SchedWrite; // Byte Order (Endianness) 64-bit Swap.
> -def WriteXCHG : SchedWrite; // Compare+Exchange - TODO RMW support.
> +defm WriteCMPXCHG : X86SchedWritePair; // Compare and set, compare and swap.
> +def WriteCMPXCHGRMW : SchedWrite; // Compare and set, compare and swap.
> +def WriteXCHG : SchedWrite; // Compare+Exchange - TODO RMW support.
>
> // Integer division.
> defm WriteDiv8 : X86SchedWritePair;
>
> Modified: llvm/trunk/lib/Target/X86/X86ScheduleAtom.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleAtom.td?rev=341024&r1=341023&r2=341024&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ScheduleAtom.td (original)
> +++ llvm/trunk/lib/Target/X86/X86ScheduleAtom.td Wed Aug 29 23:26:00 2018
> @@ -84,6 +84,8 @@ defm : AtomWriteResPair<WriteIMul64, [At
> defm : X86WriteRes<WriteXCHG, [AtomPort01], 2, [2], 1>;
> defm : X86WriteRes<WriteBSWAP32, [AtomPort0], 1, [1], 1>;
> defm : X86WriteRes<WriteBSWAP64, [AtomPort0], 1, [1], 1>;
> +defm : AtomWriteResPair<WriteCMPXCHG, [AtomPort01], [AtomPort01], 15, 15, [15]>;
> +defm : X86WriteRes<WriteCMPXCHGRMW, [AtomPort01, AtomPort0], 1, [1, 1], 1>;
>
> defm : AtomWriteResPair<WriteDiv8, [AtomPort01], [AtomPort01], 50, 68, [50], [68]>;
> defm : AtomWriteResPair<WriteDiv16, [AtomPort01], [AtomPort01], 50, 50, [50], [50]>;
> @@ -676,12 +678,6 @@ def AtomWrite01_14 : SchedWriteRes<[Atom
> }
> def : InstRW<[AtomWrite01_14], (instrs CMPXCHG16rm, CMPXCHG32rm, CMPXCHG64rm)>;
>
> -def AtomWrite01_15 : SchedWriteRes<[AtomPort01]> {
> - let Latency = 15;
> - let ResourceCycles = [15];
> -}
> -def : InstRW<[AtomWrite01_15], (instrs CMPXCHG16rr, CMPXCHG32rr, CMPXCHG64rr)>;
> -
> def AtomWrite01_17 : SchedWriteRes<[AtomPort01]> {
> let Latency = 17;
> let ResourceCycles = [17];
>
> Modified: llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td?rev=341024&r1=341023&r2=341024&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td (original)
> +++ llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td Wed Aug 29 23:26:00 2018
> @@ -170,6 +170,8 @@ defm : X86WriteRes<WriteIMulH, [JA
>
> defm : X86WriteRes<WriteBSWAP32, [JALU01], 1, [1], 1>;
> defm : X86WriteRes<WriteBSWAP64, [JALU01], 1, [1], 1>;
> +defm : X86WriteRes<WriteCMPXCHG,[JALU01], 1, [1], 1>;
> +defm : X86WriteRes<WriteCMPXCHGRMW,[JALU01, JSAGU, JLAGU], 4, [1, 1, 1], 2>;
> defm : X86WriteRes<WriteXCHG, [JALU01], 1, [1], 1>;
>
> defm : JWriteResIntPair<WriteDiv8, [JALU1, JDiv], 12, [1, 12], 1>;
>
> Modified: llvm/trunk/lib/Target/X86/X86ScheduleSLM.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleSLM.td?rev=341024&r1=341023&r2=341024&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ScheduleSLM.td (original)
> +++ llvm/trunk/lib/Target/X86/X86ScheduleSLM.td Wed Aug 29 23:26:00 2018
> @@ -100,7 +100,9 @@ defm : SLMWriteResPair<WriteIMul64, [SLM
>
> defm : X86WriteRes<WriteBSWAP32, [SLM_IEC_RSV01], 1, [1], 1>;
> defm : X86WriteRes<WriteBSWAP64, [SLM_IEC_RSV01], 1, [1], 1>;
> -defm : X86WriteRes<WriteXCHG, [SLM_IEC_RSV01], 1, [1], 1>;
> +defm : X86WriteRes<WriteCMPXCHG, [SLM_IEC_RSV01], 1, [1], 1>;
> +defm : X86WriteRes<WriteCMPXCHGRMW, [SLM_IEC_RSV01, SLM_MEC_RSV], 4, [1, 2], 2>;
> +defm : X86WriteRes<WriteXCHG, [SLM_IEC_RSV01], 1, [1], 1>;
>
> defm : SLMWriteResPair<WriteShift, [SLM_IEC_RSV0], 1>;
>
>
> Modified: llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td?rev=341024&r1=341023&r2=341024&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td (original)
> +++ llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td Wed Aug 29 23:26:00 2018
> @@ -182,6 +182,8 @@ defm : ZnWriteResPair<WriteIMul64, [ZnAL
>
> defm : X86WriteRes<WriteBSWAP32, [ZnALU], 1, [4], 1>;
> defm : X86WriteRes<WriteBSWAP64, [ZnALU], 1, [4], 1>;
> +defm : X86WriteRes<WriteCMPXCHG, [ZnALU], 1, [1], 1>;
> +defm : X86WriteRes<WriteCMPXCHGRMW,[ZnALU,ZnAGU], 8, [1,1], 5>;
> defm : X86WriteRes<WriteXCHG, [ZnALU], 1, [2], 2>;
>
> defm : ZnWriteResPair<WriteShift, [ZnALU], 1>;
> @@ -743,13 +745,6 @@ def : InstRW<[WriteMicrocoded], (instreg
> def : InstRW<[WriteMicrocoded], (instregex "SH(R|L)D(16|32|64)mrCL")>;
>
> //-- Misc instructions --//
> -// CMPXCHG.
> -def ZnWriteCMPXCHG : SchedWriteRes<[ZnAGU, ZnALU]> {
> - let Latency = 8;
> - let NumMicroOps = 5;
> -}
> -def : InstRW<[ZnWriteCMPXCHG], (instregex "CMPXCHG(8|16|32|64)rm")>;
> -
> // CMPXCHG8B.
> def ZnWriteCMPXCHG8B : SchedWriteRes<[ZnAGU, ZnALU]> {
> let NumMicroOps = 18;
>
> Modified: llvm/trunk/test/CodeGen/X86/schedule-x86_64.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/schedule-x86_64.ll?rev=341024&r1=341023&r2=341024&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/schedule-x86_64.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/schedule-x86_64.ll Wed Aug 29 23:26:00 2018
> @@ -4307,7 +4307,7 @@ define void @test_cmpxchg_8(i8 %a0, i8 %
> ; GENERIC: # %bb.0:
> ; GENERIC-NEXT: #APP
> ; GENERIC-NEXT: cmpxchgb %dil, %sil # sched: [5:1.33]
> -; GENERIC-NEXT: cmpxchgb %dil, (%rdx) # sched: [8:1.00]
> +; GENERIC-NEXT: cmpxchgb %dil, (%rdx) # sched: [8:2.00]
> ; GENERIC-NEXT: #NO_APP
> ; GENERIC-NEXT: retq # sched: [1:1.00]
> ;
> @@ -4331,7 +4331,7 @@ define void @test_cmpxchg_8(i8 %a0, i8 %
> ; SANDY: # %bb.0:
> ; SANDY-NEXT: #APP
> ; SANDY-NEXT: cmpxchgb %dil, %sil # sched: [5:1.33]
> -; SANDY-NEXT: cmpxchgb %dil, (%rdx) # sched: [8:1.00]
> +; SANDY-NEXT: cmpxchgb %dil, (%rdx) # sched: [8:2.00]
> ; SANDY-NEXT: #NO_APP
> ; SANDY-NEXT: retq # sched: [1:1.00]
> ;
> @@ -4390,7 +4390,7 @@ define void @test_cmpxchg_16(i16 %a0, i1
> ; GENERIC: # %bb.0:
> ; GENERIC-NEXT: #APP
> ; GENERIC-NEXT: cmpxchgw %di, %si # sched: [5:1.33]
> -; GENERIC-NEXT: cmpxchgw %di, (%rdx) # sched: [8:1.00]
> +; GENERIC-NEXT: cmpxchgw %di, (%rdx) # sched: [8:2.00]
> ; GENERIC-NEXT: #NO_APP
> ; GENERIC-NEXT: retq # sched: [1:1.00]
> ;
> @@ -4414,7 +4414,7 @@ define void @test_cmpxchg_16(i16 %a0, i1
> ; SANDY: # %bb.0:
> ; SANDY-NEXT: #APP
> ; SANDY-NEXT: cmpxchgw %di, %si # sched: [5:1.33]
> -; SANDY-NEXT: cmpxchgw %di, (%rdx) # sched: [8:1.00]
> +; SANDY-NEXT: cmpxchgw %di, (%rdx) # sched: [8:2.00]
> ; SANDY-NEXT: #NO_APP
> ; SANDY-NEXT: retq # sched: [1:1.00]
> ;
> @@ -4473,7 +4473,7 @@ define void @test_cmpxchg_32(i32 %a0, i3
> ; GENERIC: # %bb.0:
> ; GENERIC-NEXT: #APP
> ; GENERIC-NEXT: cmpxchgl %edi, %esi # sched: [5:1.33]
> -; GENERIC-NEXT: cmpxchgl %edi, (%rdx) # sched: [8:1.00]
> +; GENERIC-NEXT: cmpxchgl %edi, (%rdx) # sched: [8:2.00]
> ; GENERIC-NEXT: #NO_APP
> ; GENERIC-NEXT: retq # sched: [1:1.00]
> ;
> @@ -4497,7 +4497,7 @@ define void @test_cmpxchg_32(i32 %a0, i3
> ; SANDY: # %bb.0:
> ; SANDY-NEXT: #APP
> ; SANDY-NEXT: cmpxchgl %edi, %esi # sched: [5:1.33]
> -; SANDY-NEXT: cmpxchgl %edi, (%rdx) # sched: [8:1.00]
> +; SANDY-NEXT: cmpxchgl %edi, (%rdx) # sched: [8:2.00]
> ; SANDY-NEXT: #NO_APP
> ; SANDY-NEXT: retq # sched: [1:1.00]
> ;
> @@ -4556,7 +4556,7 @@ define void @test_cmpxchg_64(i64 %a0, i6
> ; GENERIC: # %bb.0:
> ; GENERIC-NEXT: #APP
> ; GENERIC-NEXT: cmpxchgq %rdi, %rsi # sched: [5:1.33]
> -; GENERIC-NEXT: cmpxchgq %rdi, (%rdx) # sched: [8:1.00]
> +; GENERIC-NEXT: cmpxchgq %rdi, (%rdx) # sched: [8:2.00]
> ; GENERIC-NEXT: #NO_APP
> ; GENERIC-NEXT: retq # sched: [1:1.00]
> ;
> @@ -4580,7 +4580,7 @@ define void @test_cmpxchg_64(i64 %a0, i6
> ; SANDY: # %bb.0:
> ; SANDY-NEXT: #APP
> ; SANDY-NEXT: cmpxchgq %rdi, %rsi # sched: [5:1.33]
> -; SANDY-NEXT: cmpxchgq %rdi, (%rdx) # sched: [8:1.00]
> +; SANDY-NEXT: cmpxchgq %rdi, (%rdx) # sched: [8:2.00]
> ; SANDY-NEXT: #NO_APP
> ; SANDY-NEXT: retq # sched: [1:1.00]
> ;
>
> Modified: llvm/trunk/test/tools/llvm-mca/X86/Generic/resources-x86_64.s
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/tools/llvm-mca/X86/Generic/resources-x86_64.s?rev=341024&r1=341023&r2=341024&view=diff
> ==============================================================================
> --- llvm/trunk/test/tools/llvm-mca/X86/Generic/resources-x86_64.s (original)
> +++ llvm/trunk/test/tools/llvm-mca/X86/Generic/resources-x86_64.s Wed Aug 29 23:26:00 2018
> @@ -1057,13 +1057,13 @@ xorq (%rax), %rdi
> # CHECK-NEXT: 5 8 1.00 U cmpsl %es:(%rdi), (%rsi)
> # CHECK-NEXT: 5 8 1.00 U cmpsq %es:(%rdi), (%rsi)
> # CHECK-NEXT: 4 5 1.33 cmpxchgb %cl, %bl
> -# CHECK-NEXT: 4 8 1.00 * * cmpxchgb %cl, (%rbx)
> +# CHECK-NEXT: 6 8 2.00 * * cmpxchgb %cl, (%rbx)
> # CHECK-NEXT: 4 5 1.33 cmpxchgw %cx, %bx
> -# CHECK-NEXT: 4 8 1.00 * * cmpxchgw %cx, (%rbx)
> +# CHECK-NEXT: 6 8 2.00 * * cmpxchgw %cx, (%rbx)
> # CHECK-NEXT: 4 5 1.33 cmpxchgl %ecx, %ebx
> -# CHECK-NEXT: 4 8 1.00 * * cmpxchgl %ecx, (%rbx)
> +# CHECK-NEXT: 6 8 2.00 * * cmpxchgl %ecx, (%rbx)
> # CHECK-NEXT: 4 5 1.33 cmpxchgq %rcx, %rbx
> -# CHECK-NEXT: 4 8 1.00 * * cmpxchgq %rcx, (%rbx)
> +# CHECK-NEXT: 6 8 2.00 * * cmpxchgq %rcx, (%rbx)
> # CHECK-NEXT: 1 100 0.33 U cpuid
> # CHECK-NEXT: 1 1 0.33 decb %dil
> # CHECK-NEXT: 3 7 1.00 * * decb (%rax)
> @@ -1620,7 +1620,7 @@ xorq (%rax), %rdi
>
> # CHECK: Resource pressure per iteration:
> # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1]
> -# CHECK-NEXT: 160.00 - 438.50 224.00 242.00 430.50 290.00 290.00
> +# CHECK-NEXT: 160.00 - 435.83 221.33 246.00 435.83 292.00 292.00
>
> # CHECK: Resource pressure by instruction:
> # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions:
> @@ -1820,13 +1820,13 @@ xorq (%rax), %rdi
> # CHECK-NEXT: - - 1.00 1.00 - 1.00 1.00 1.00 cmpsl %es:(%rdi), (%rsi)
> # CHECK-NEXT: - - 1.00 1.00 - 1.00 1.00 1.00 cmpsq %es:(%rdi), (%rsi)
> # CHECK-NEXT: - - 1.50 1.00 - 1.50 - - cmpxchgb %cl, %bl
> -# CHECK-NEXT: - - 1.00 1.00 - 1.00 0.50 0.50 cmpxchgb %cl, (%rbx)
> +# CHECK-NEXT: - - 0.33 0.33 1.00 2.33 1.00 1.00 cmpxchgb %cl, (%rbx)
> # CHECK-NEXT: - - 1.50 1.00 - 1.50 - - cmpxchgw %cx, %bx
> -# CHECK-NEXT: - - 1.00 1.00 - 1.00 0.50 0.50 cmpxchgw %cx, (%rbx)
> +# CHECK-NEXT: - - 0.33 0.33 1.00 2.33 1.00 1.00 cmpxchgw %cx, (%rbx)
> # CHECK-NEXT: - - 1.50 1.00 - 1.50 - - cmpxchgl %ecx, %ebx
> -# CHECK-NEXT: - - 1.00 1.00 - 1.00 0.50 0.50 cmpxchgl %ecx, (%rbx)
> +# CHECK-NEXT: - - 0.33 0.33 1.00 2.33 1.00 1.00 cmpxchgl %ecx, (%rbx)
> # CHECK-NEXT: - - 1.50 1.00 - 1.50 - - cmpxchgq %rcx, %rbx
> -# CHECK-NEXT: - - 1.00 1.00 - 1.00 0.50 0.50 cmpxchgq %rcx, (%rbx)
> +# CHECK-NEXT: - - 0.33 0.33 1.00 2.33 1.00 1.00 cmpxchgq %rcx, (%rbx)
> # CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cpuid
> # CHECK-NEXT: - - 0.33 0.33 - 0.33 - - decb %dil
> # CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 decb (%rax)
>
> Modified: llvm/trunk/test/tools/llvm-mca/X86/SandyBridge/resources-x86_64.s
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/tools/llvm-mca/X86/SandyBridge/resources-x86_64.s?rev=341024&r1=341023&r2=341024&view=diff
> ==============================================================================
> --- llvm/trunk/test/tools/llvm-mca/X86/SandyBridge/resources-x86_64.s (original)
> +++ llvm/trunk/test/tools/llvm-mca/X86/SandyBridge/resources-x86_64.s Wed Aug 29 23:26:00 2018
> @@ -852,6 +852,8 @@ xorq %rsi, %rdi
> xorq %rsi, (%rax)
> xorq (%rax), %rdi
>
> +# CCHECK-NEXT: 160.00 - 439.83 221.33 250.00 431.83 294.00 294.00
> +
> # CHECK: Instruction Info:
> # CHECK-NEXT: [1]: #uOps
> # CHECK-NEXT: [2]: Latency
> @@ -1057,13 +1059,13 @@ xorq (%rax), %rdi
> # CHECK-NEXT: 5 8 1.00 U cmpsl %es:(%rdi), (%rsi)
> # CHECK-NEXT: 5 8 1.00 U cmpsq %es:(%rdi), (%rsi)
> # CHECK-NEXT: 4 5 1.33 cmpxchgb %cl, %bl
> -# CHECK-NEXT: 4 8 1.00 * * cmpxchgb %cl, (%rbx)
> +# CHECK-NEXT: 6 8 2.00 * * cmpxchgb %cl, (%rbx)
> # CHECK-NEXT: 4 5 1.33 cmpxchgw %cx, %bx
> -# CHECK-NEXT: 4 8 1.00 * * cmpxchgw %cx, (%rbx)
> +# CHECK-NEXT: 6 8 2.00 * * cmpxchgw %cx, (%rbx)
> # CHECK-NEXT: 4 5 1.33 cmpxchgl %ecx, %ebx
> -# CHECK-NEXT: 4 8 1.00 * * cmpxchgl %ecx, (%rbx)
> +# CHECK-NEXT: 6 8 2.00 * * cmpxchgl %ecx, (%rbx)
> # CHECK-NEXT: 4 5 1.33 cmpxchgq %rcx, %rbx
> -# CHECK-NEXT: 4 8 1.00 * * cmpxchgq %rcx, (%rbx)
> +# CHECK-NEXT: 6 8 2.00 * * cmpxchgq %rcx, (%rbx)
> # CHECK-NEXT: 1 100 0.33 U cpuid
> # CHECK-NEXT: 1 1 0.33 decb %dil
> # CHECK-NEXT: 3 7 1.00 * * decb (%rax)
> @@ -1620,7 +1622,7 @@ xorq (%rax), %rdi
>
> # CHECK: Resource pressure per iteration:
> # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1]
> -# CHECK-NEXT: 160.00 - 438.50 224.00 242.00 430.50 290.00 290.00
> +# CHECK-NEXT: 160.00 - 435.83 221.33 246.00 435.83 292.00 292.00
>
> # CHECK: Resource pressure by instruction:
> # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions:
> @@ -1820,13 +1822,13 @@ xorq (%rax), %rdi
> # CHECK-NEXT: - - 1.00 1.00 - 1.00 1.00 1.00 cmpsl %es:(%rdi), (%rsi)
> # CHECK-NEXT: - - 1.00 1.00 - 1.00 1.00 1.00 cmpsq %es:(%rdi), (%rsi)
> # CHECK-NEXT: - - 1.50 1.00 - 1.50 - - cmpxchgb %cl, %bl
> -# CHECK-NEXT: - - 1.00 1.00 - 1.00 0.50 0.50 cmpxchgb %cl, (%rbx)
> +# CHECK-NEXT: - - 0.33 0.33 1.00 2.33 1.00 1.00 cmpxchgb %cl, (%rbx)
> # CHECK-NEXT: - - 1.50 1.00 - 1.50 - - cmpxchgw %cx, %bx
> -# CHECK-NEXT: - - 1.00 1.00 - 1.00 0.50 0.50 cmpxchgw %cx, (%rbx)
> +# CHECK-NEXT: - - 0.33 0.33 1.00 2.33 1.00 1.00 cmpxchgw %cx, (%rbx)
> # CHECK-NEXT: - - 1.50 1.00 - 1.50 - - cmpxchgl %ecx, %ebx
> -# CHECK-NEXT: - - 1.00 1.00 - 1.00 0.50 0.50 cmpxchgl %ecx, (%rbx)
> +# CHECK-NEXT: - - 0.33 0.33 1.00 2.33 1.00 1.00 cmpxchgl %ecx, (%rbx)
> # CHECK-NEXT: - - 1.50 1.00 - 1.50 - - cmpxchgq %rcx, %rbx
> -# CHECK-NEXT: - - 1.00 1.00 - 1.00 0.50 0.50 cmpxchgq %rcx, (%rbx)
> +# CHECK-NEXT: - - 0.33 0.33 1.00 2.33 1.00 1.00 cmpxchgq %rcx, (%rbx)
> # CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cpuid
> # CHECK-NEXT: - - 0.33 0.33 - 0.33 - - decb %dil
> # CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 decb (%rax)
>
>
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