[PATCH] D51492: [X86][BtVer2] Fix WriteFShuffle256 schedule write info.

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added a comment.

[MCA can get the latency, and micro-ops for the most part, but ]

> processor resource cycles

Really ignorant question: how do you decide what is the right values?
Is there some documentation?


https://reviews.llvm.org/D51492