[PATCH] D39386: [Power9] Allow gpr callee saved spills in prologue to vector registers rather than stack

[Francis Visoiu Mistrih via Phabricator via llvm-commits]

thegameg added inline comments.


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Comment at: llvm/test/CodeGen/MIR/PowerPC/prolog_vec_spills.mir:18
+# CHECK-LABEL: name:            test1BB
+# CHECK: body:             |
+# CHECK: $f1 = MTVSRD killed $x14
----------------
This line is probably not needed.


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Comment at: llvm/test/CodeGen/MIR/PowerPC/prolog_vec_spills.mir:55
+# CHECK-LABEL: name:            test2BB
+# CHECK: body:             |
+# CHECK: $f0 = MTVSRD killed $x14
----------------
Same.


https://reviews.llvm.org/D39386