[PATCH] D49778: Fix "Q" and "R" inline assembly template modifiers for big-endian Arm

[Florian Hahn via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL341052: Fix "Q" and "R" inline assembly template modifiers for big-endian Arm (authored by fhahn, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D49778?vs=163081&id=163293#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D49778

Files:
  llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
  llvm/trunk/test/CodeGen/ARM/print-registers.ll


Index: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
===================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -367,6 +367,18 @@
 
       unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
       unsigned RC;
+      bool FirstHalf;
+      const ARMBaseTargetMachine &ATM =
+        static_cast<const ARMBaseTargetMachine &>(TM);
+
+      // 'Q' should correspond to the low order register and 'R' to the high
+      // order register.  Whether this corresponds to the upper or lower half
+      // depends on the endianess mode.
+      if (ExtraCode[0] == 'Q')
+        FirstHalf = ATM.isLittleEndian();
+      else
+        // ExtraCode[0] == 'R'.
+        FirstHalf = !ATM.isLittleEndian();
       const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
       if (InlineAsm::hasRegClassConstraint(Flags, RC) &&
           ARM::GPRPairRegClass.hasSubClassEq(TRI->getRegClass(RC))) {
@@ -376,14 +388,14 @@
         if (!MO.isReg())
           return true;
         const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
-        unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
+        unsigned Reg = TRI->getSubReg(MO.getReg(), FirstHalf ?
             ARM::gsub_0 : ARM::gsub_1);
         O << ARMInstPrinter::getRegisterName(Reg);
         return false;
       }
       if (NumVals != 2)
         return true;
-      unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
+      unsigned RegOp = FirstHalf ? OpNum : OpNum + 1;
       if (RegOp >= MI->getNumOperands())
         return true;
       const MachineOperand &MO = MI->getOperand(RegOp);
Index: llvm/trunk/test/CodeGen/ARM/print-registers.ll
===================================================================
--- llvm/trunk/test/CodeGen/ARM/print-registers.ll
+++ llvm/trunk/test/CodeGen/ARM/print-registers.ll
@@ -0,0 +1,10 @@
+; RUN: llc -mtriple=armeb-arm-none-eabi < %s -o -| FileCheck %s -check-prefixes=CHECK-BE
+; RUN: llc -mtriple=arm-arm-none-eabi < %s -o -| FileCheck %s -check-prefixes=CHECK-LE
+
+define dso_local void @_Z3fooi(i32 %a) local_unnamed_addr #0 {
+entry:
+; CHECK-BE: @ plain: [[LOW_REG:r[0-9]+]] Q: [[HIGH_REG:r[0-9]+]] R: [[LOW_REG]] H: [[HIGH_REG]]
+; CHECK-LE: @ plain: [[LOW_REG:r[0-9]+]] Q: [[LOW_REG]] R: [[HIGH_REG:r[0-9]+]] H: [[HIGH_REG]]
+  tail call void asm sideeffect "// plain: $0 Q: ${0:Q} R: ${0:R} H: ${0:H}", "r"(i64 1) #1
+  ret void
+}


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