[PATCH] D51371: [WebAssembly][NFC] Document stackifier tablegen backend
Thomas Lively via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 28 11:50:53 PDT 2018
This revision was automatically updated to reflect the committed changes.
Closed by commit rL340864: [WebAssembly][NFC] Document stackifier tablegen backend (authored by tlively, committed by ).
Repository:
rL LLVM
https://reviews.llvm.org/D51371
Files:
llvm/trunk/lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp
llvm/trunk/utils/TableGen/WebAssemblyStackifierEmitter.cpp
Index: llvm/trunk/utils/TableGen/WebAssemblyStackifierEmitter.cpp
===================================================================
--- llvm/trunk/utils/TableGen/WebAssemblyStackifierEmitter.cpp
+++ llvm/trunk/utils/TableGen/WebAssemblyStackifierEmitter.cpp
@@ -17,6 +17,17 @@
namespace llvm {
+// Find all register WebAssembly instructions and their corresponding stack
+// instructions. For each pair, emit a switch case of the form
+//
+// case WebAssembly::RegisterInstr: return WebAssembly::StackInstr;
+//
+// For example,
+//
+// case WebAssembly::ADD_I32: return WebAssembly::ADD_I32_S;
+//
+// This is useful for converting instructions from their register form to their
+// equivalent stack form.
void EmitWebAssemblyStackifier(RecordKeeper &RK, raw_ostream &OS) {
Record *InstrClass = RK.getClass("WebAssemblyInst");
for (auto &RecordPair : RK.getDefs()) {
@@ -26,7 +37,7 @@
if (IsStackBased)
continue;
OS << " case WebAssembly::" << RecordPair.first << ": return "
- << "WebAssembly::" << RecordPair.first << "_S; break;\n";
+ << "WebAssembly::" << RecordPair.first << "_S;\n";
}
}
Index: llvm/trunk/lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp
===================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp
@@ -285,8 +285,13 @@
static unsigned regInstructionToStackInstruction(unsigned OpCode) {
// For most opcodes, this function could have been implemented as "return
// OpCode + 1", but since table-gen alphabetically sorts them, this cannot be
- // guaranteed (see e.g. BR and BR_IF), so we table-gen a giant switch
- // statement instead.
+ // guaranteed (see e.g. BR and BR_IF). Instead we use a giant switch statement
+ // generated by a custom TableGen backend (WebAssemblyStackifierEmitter.cpp)
+ // that emits switch cases of the form
+ //
+ // case WebAssembly::RegisterInstr: return WebAssembly::StackInstr;
+ //
+ // for every pair of equivalent register and stack instructions.
switch (OpCode) {
default:
llvm_unreachable(
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