[PATCH] D51371: [WebAssembly][NFC] Document stackifier tablegen backend

[Thomas Lively via Phabricator via llvm-commits]

tlively created this revision.
tlively added reviewers: dschuff, aheejin.
Herald added subscribers: llvm-commits, sunfish, jgravelle-google, sbc100.

Add comments to help readers avoid having to read tablegen backends to
understand the code. Also remove unecessary breaks from the output.


Repository:
  rL LLVM

https://reviews.llvm.org/D51371

Files:
  lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp
  utils/TableGen/WebAssemblyStackifierEmitter.cpp


Index: utils/TableGen/WebAssemblyStackifierEmitter.cpp
===================================================================
--- utils/TableGen/WebAssemblyStackifierEmitter.cpp
+++ utils/TableGen/WebAssemblyStackifierEmitter.cpp
@@ -17,14 +17,21 @@
 
 namespace llvm {
 
+// Find all register WebAssembly instructions and their corresponding stack
+// instructions. For each pair, emit a switch case of the form
+//
+//   case WebAssembly::RegisterInstr: return WebAssembly::StackInstr;
+//
+// This is useful for converting instructions from their register form to their
+// equivalent stack form.
 void EmitWebAssemblyStackifier(RecordKeeper &RK, raw_ostream &OS) {
   Record *InstrClass = RK.getClass("WebAssemblyInst");
   for (auto &RecordPair : RK.getDefs()) {
     if (!RecordPair.second->isSubClassOf(InstrClass)) continue;
     bool IsStackBased = RecordPair.second->getValueAsBit("StackBased");
     if (IsStackBased) continue;
     OS << "  case WebAssembly::" << RecordPair.first << ": return "
-       << "WebAssembly::" << RecordPair.first << "_S; break;\n";
+       << "WebAssembly::" << RecordPair.first << "_S;\n";
   }
 }
 
Index: lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp
===================================================================
--- lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp
+++ lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp
@@ -285,8 +285,13 @@
 static unsigned regInstructionToStackInstruction(unsigned OpCode) {
   // For most opcodes, this function could have been implemented as "return
   // OpCode + 1", but since table-gen alphabetically sorts them, this cannot be
-  // guaranteed (see e.g. BR and BR_IF), so we table-gen a giant switch
-  // statement instead.
+  // guaranteed (see e.g. BR and BR_IF). Instead we use a giant switch statement
+  // generated by a custom TableGen backend (WebAssemblyStackifierEmitter.cpp)
+  // that emits switch cases of the form
+  //
+  //   case WebAssembly::RegisterInstr: return WebAssembly::StackInstr;
+  //
+  // for every pair of equivalent register and stack instructions.
   switch (OpCode) {
   default:
     llvm_unreachable(


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