[llvm] r340733 - [Sparc] Add support for the cycle counter available in GR740
Daniel Cederman via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 27 04:11:47 PDT 2018
Author: dcederman
Date: Mon Aug 27 04:11:47 2018
New Revision: 340733
URL: http://llvm.org/viewvc/llvm-project?rev=340733&view=rev
Log:
[Sparc] Add support for the cycle counter available in GR740
Summary: The GR740 provides an up cycle counter in the registers ASR22
and ASR23. As these registers can not be read together atomically we only
use the value of ASR23 for llvm.readcyclecounter(). The ASR23 register
holds the 32 LSBs of the up-counter.
Reviewers: jyknight, venkatra
Reviewed By: jyknight
Subscribers: jfb, fedor.sergeev, jrtc27, llvm-commits
Differential Revision: https://reviews.llvm.org/D48638
Added:
llvm/trunk/test/CodeGen/SPARC/readcycle.ll
Modified:
llvm/trunk/lib/Target/Sparc/LeonFeatures.td
llvm/trunk/lib/Target/Sparc/Sparc.td
llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp
llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp
llvm/trunk/lib/Target/Sparc/SparcSubtarget.h
Modified: llvm/trunk/lib/Target/Sparc/LeonFeatures.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/LeonFeatures.td?rev=340733&r1=340732&r2=340733&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/LeonFeatures.td (original)
+++ llvm/trunk/lib/Target/Sparc/LeonFeatures.td Mon Aug 27 04:11:47 2018
@@ -58,3 +58,7 @@ def FixAllFDIVSQRT : SubtargetFeature<
"true",
"LEON erratum fix: Fix FDIVS/FDIVD/FSQRTS/FSQRTD instructions with NOPs and floating-point store"
>;
+
+def LeonCycleCounter
+ : SubtargetFeature<"leoncyclecounter", "HasLeonCycleCounter", "true",
+ "Use the Leon cycle counter register">;
Modified: llvm/trunk/lib/Target/Sparc/Sparc.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/Sparc.td?rev=340733&r1=340732&r2=340733&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/Sparc.td (original)
+++ llvm/trunk/lib/Target/Sparc/Sparc.td Mon Aug 27 04:11:47 2018
@@ -159,7 +159,7 @@ def : Processor<"leon4", LEON4Itinerarie
// LEON 4 FT (GR740)
// TO DO: Place-holder: Processor specific features will be added *very* soon here.
def : Processor<"gr740", LEON4Itineraries,
- [FeatureLeon, UMACSMACSupport, LeonCASA]>;
+ [FeatureLeon, UMACSMACSupport, LeonCASA, LeonCycleCounter]>;
//===----------------------------------------------------------------------===//
// Declare the target which we are implementing
Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=340733&r1=340732&r2=340733&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Mon Aug 27 04:11:47 2018
@@ -1803,6 +1803,9 @@ SparcTargetLowering::SparcTargetLowering
if (!Subtarget->is64Bit())
setTargetDAGCombine(ISD::BITCAST);
+ if (Subtarget->hasLeonCycleCounter())
+ setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
+
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
setMinFunctionAlignment(2);
@@ -3578,7 +3581,16 @@ void SparcTargetLowering::ReplaceNodeRes
getLibcallName(libCall),
1));
return;
-
+ case ISD::READCYCLECOUNTER: {
+ assert(Subtarget->hasLeonCycleCounter());
+ SDValue Lo = DAG.getCopyFromReg(N->getOperand(0), dl, SP::ASR23, MVT::i32);
+ SDValue Hi = DAG.getCopyFromReg(Lo, dl, SP::G0, MVT::i32);
+ SDValue Ops[] = { Lo, Hi };
+ SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops);
+ Results.push_back(Pair);
+ Results.push_back(N->getOperand(0));
+ return;
+ }
case ISD::SINT_TO_FP:
case ISD::UINT_TO_FP:
// Custom lower only if it involves f128 or i64.
Modified: llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp?rev=340733&r1=340732&r2=340733&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp Mon Aug 27 04:11:47 2018
@@ -95,6 +95,10 @@ BitVector SparcRegisterInfo::getReserved
}
}
+ // Reserve ASR1-ASR31
+ for (unsigned n = 0; n < 31; n++)
+ Reserved.set(SP::ASR1 + n);
+
return Reserved;
}
Modified: llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp?rev=340733&r1=340732&r2=340733&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp Mon Aug 27 04:11:47 2018
@@ -47,6 +47,7 @@ SparcSubtarget &SparcSubtarget::initiali
InsertNOPLoad = false;
FixAllFDIVSQRT = false;
DetectRoundChange = false;
+ HasLeonCycleCounter = false;
// Determine default and user specified characteristics
std::string CPUName = CPU;
Modified: llvm/trunk/lib/Target/Sparc/SparcSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcSubtarget.h?rev=340733&r1=340732&r2=340733&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcSubtarget.h (original)
+++ llvm/trunk/lib/Target/Sparc/SparcSubtarget.h Mon Aug 27 04:11:47 2018
@@ -50,6 +50,7 @@ class SparcSubtarget : public SparcGenSu
bool InsertNOPLoad;
bool FixAllFDIVSQRT;
bool DetectRoundChange;
+ bool HasLeonCycleCounter;
SparcInstrInfo InstrInfo;
SparcTargetLowering TLInfo;
@@ -95,6 +96,7 @@ public:
bool insertNOPLoad() const { return InsertNOPLoad; }
bool fixAllFDIVSQRT() const { return FixAllFDIVSQRT; }
bool detectRoundChange() const { return DetectRoundChange; }
+ bool hasLeonCycleCounter() const { return HasLeonCycleCounter; }
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
Added: llvm/trunk/test/CodeGen/SPARC/readcycle.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SPARC/readcycle.ll?rev=340733&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/SPARC/readcycle.ll (added)
+++ llvm/trunk/test/CodeGen/SPARC/readcycle.ll Mon Aug 27 04:11:47 2018
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=sparc -mcpu=gr740 -verify-machineinstrs | FileCheck %s
+; CHECK: rd %asr23, %o1
+; CHECK: mov %g0, %o0
+
+define i64 @test() {
+entry:
+ %0 = call i64 @llvm.readcyclecounter()
+ ret i64 %0
+}
+
+declare i64 @llvm.readcyclecounter()
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