[llvm] r340722 - [RISCV] atomic_store_nn have a different layout to regular store
Roger Ferrer Ibanez via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 27 00:08:18 PDT 2018
Author: rogfer01
Date: Mon Aug 27 00:08:18 2018
New Revision: 340722
URL: http://llvm.org/viewvc/llvm-project?rev=340722&view=rev
Log:
[RISCV] atomic_store_nn have a different layout to regular store
We cannot directy reuse the patterns of StPat because for some reason the store
DAG node and the atomic_store_nn DAG nodes put the ptr and the value in
different positions. Currently we attempt to store the address to an address
formed by the value.
Differential Revision: https://reviews.llvm.org/D51217
Modified:
llvm/trunk/lib/Target/RISCV/RISCVInstrInfoA.td
llvm/trunk/test/CodeGen/RISCV/atomic-load-store.ll
Modified: llvm/trunk/lib/Target/RISCV/RISCVInstrInfoA.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVInstrInfoA.td?rev=340722&r1=340721&r2=340722&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVInstrInfoA.td (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVInstrInfoA.td Mon Aug 27 00:08:18 2018
@@ -44,6 +44,17 @@ multiclass AMO_rr_aq_rl<bits<5> funct5,
def _AQ_RL : AMO_rr<funct5, 1, 1, funct3, opcodestr # ".aqrl">;
}
+multiclass AtomicStPat<PatFrag StoreOp, RVInst Inst, RegisterClass StTy> {
+ def : Pat<(StoreOp GPR:$rs1, StTy:$rs2), (Inst StTy:$rs2, GPR:$rs1, 0)>;
+ def : Pat<(StoreOp AddrFI:$rs1, StTy:$rs2), (Inst StTy:$rs2, AddrFI:$rs1, 0)>;
+ def : Pat<(StoreOp (add GPR:$rs1, simm12:$imm12), StTy:$rs2),
+ (Inst StTy:$rs2, GPR:$rs1, simm12:$imm12)>;
+ def : Pat<(StoreOp (add AddrFI:$rs1, simm12:$imm12), StTy:$rs2),
+ (Inst StTy:$rs2, AddrFI:$rs1, simm12:$imm12)>;
+ def : Pat<(StoreOp (IsOrAdd AddrFI:$rs1, simm12:$imm12), StTy:$rs2),
+ (Inst StTy:$rs2, AddrFI:$rs1, simm12:$imm12)>;
+}
+
//===----------------------------------------------------------------------===//
// Instructions
//===----------------------------------------------------------------------===//
@@ -91,7 +102,7 @@ defm : LdPat<atomic_load_8, LB>;
defm : LdPat<atomic_load_16, LH>;
defm : LdPat<atomic_load_32, LW>;
-defm : StPat<atomic_store_8, SB, GPR>;
-defm : StPat<atomic_store_16, SH, GPR>;
-defm : StPat<atomic_store_32, SW, GPR>;
-} // Predicates = [HasStdExtF]
+defm : AtomicStPat<atomic_store_8, SB, GPR>;
+defm : AtomicStPat<atomic_store_16, SH, GPR>;
+defm : AtomicStPat<atomic_store_32, SW, GPR>;
+} // Predicates = [HasStdExtA]
Modified: llvm/trunk/test/CodeGen/RISCV/atomic-load-store.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/atomic-load-store.ll?rev=340722&r1=340721&r2=340722&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/atomic-load-store.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/atomic-load-store.ll Mon Aug 27 00:08:18 2018
@@ -350,7 +350,7 @@ define void @atomic_store_i8_unordered(i
;
; RV32IA-LABEL: atomic_store_i8_unordered:
; RV32IA: # %bb.0:
-; RV32IA-NEXT: sb a0, 0(a1)
+; RV32IA-NEXT: sb a1, 0(a0)
; RV32IA-NEXT: ret
store atomic i8 %b, i8* %a unordered, align 1
ret void
@@ -369,7 +369,7 @@ define void @atomic_store_i8_monotonic(i
;
; RV32IA-LABEL: atomic_store_i8_monotonic:
; RV32IA: # %bb.0:
-; RV32IA-NEXT: sb a0, 0(a1)
+; RV32IA-NEXT: sb a1, 0(a0)
; RV32IA-NEXT: ret
store atomic i8 %b, i8* %a monotonic, align 1
ret void
@@ -389,7 +389,7 @@ define void @atomic_store_i8_release(i8
; RV32IA-LABEL: atomic_store_i8_release:
; RV32IA: # %bb.0:
; RV32IA-NEXT: fence rw, w
-; RV32IA-NEXT: sb a0, 0(a1)
+; RV32IA-NEXT: sb a1, 0(a0)
; RV32IA-NEXT: ret
store atomic i8 %b, i8* %a release, align 1
ret void
@@ -409,7 +409,7 @@ define void @atomic_store_i8_seq_cst(i8
; RV32IA-LABEL: atomic_store_i8_seq_cst:
; RV32IA: # %bb.0:
; RV32IA-NEXT: fence rw, w
-; RV32IA-NEXT: sb a0, 0(a1)
+; RV32IA-NEXT: sb a1, 0(a0)
; RV32IA-NEXT: ret
store atomic i8 %b, i8* %a seq_cst, align 1
ret void
@@ -428,7 +428,7 @@ define void @atomic_store_i16_unordered(
;
; RV32IA-LABEL: atomic_store_i16_unordered:
; RV32IA: # %bb.0:
-; RV32IA-NEXT: sh a0, 0(a1)
+; RV32IA-NEXT: sh a1, 0(a0)
; RV32IA-NEXT: ret
store atomic i16 %b, i16* %a unordered, align 2
ret void
@@ -447,7 +447,7 @@ define void @atomic_store_i16_monotonic(
;
; RV32IA-LABEL: atomic_store_i16_monotonic:
; RV32IA: # %bb.0:
-; RV32IA-NEXT: sh a0, 0(a1)
+; RV32IA-NEXT: sh a1, 0(a0)
; RV32IA-NEXT: ret
store atomic i16 %b, i16* %a monotonic, align 2
ret void
@@ -467,7 +467,7 @@ define void @atomic_store_i16_release(i1
; RV32IA-LABEL: atomic_store_i16_release:
; RV32IA: # %bb.0:
; RV32IA-NEXT: fence rw, w
-; RV32IA-NEXT: sh a0, 0(a1)
+; RV32IA-NEXT: sh a1, 0(a0)
; RV32IA-NEXT: ret
store atomic i16 %b, i16* %a release, align 2
ret void
@@ -487,7 +487,7 @@ define void @atomic_store_i16_seq_cst(i1
; RV32IA-LABEL: atomic_store_i16_seq_cst:
; RV32IA: # %bb.0:
; RV32IA-NEXT: fence rw, w
-; RV32IA-NEXT: sh a0, 0(a1)
+; RV32IA-NEXT: sh a1, 0(a0)
; RV32IA-NEXT: ret
store atomic i16 %b, i16* %a seq_cst, align 2
ret void
@@ -506,7 +506,7 @@ define void @atomic_store_i32_unordered(
;
; RV32IA-LABEL: atomic_store_i32_unordered:
; RV32IA: # %bb.0:
-; RV32IA-NEXT: sw a0, 0(a1)
+; RV32IA-NEXT: sw a1, 0(a0)
; RV32IA-NEXT: ret
store atomic i32 %b, i32* %a unordered, align 4
ret void
@@ -525,7 +525,7 @@ define void @atomic_store_i32_monotonic(
;
; RV32IA-LABEL: atomic_store_i32_monotonic:
; RV32IA: # %bb.0:
-; RV32IA-NEXT: sw a0, 0(a1)
+; RV32IA-NEXT: sw a1, 0(a0)
; RV32IA-NEXT: ret
store atomic i32 %b, i32* %a monotonic, align 4
ret void
@@ -545,7 +545,7 @@ define void @atomic_store_i32_release(i3
; RV32IA-LABEL: atomic_store_i32_release:
; RV32IA: # %bb.0:
; RV32IA-NEXT: fence rw, w
-; RV32IA-NEXT: sw a0, 0(a1)
+; RV32IA-NEXT: sw a1, 0(a0)
; RV32IA-NEXT: ret
store atomic i32 %b, i32* %a release, align 4
ret void
@@ -565,7 +565,7 @@ define void @atomic_store_i32_seq_cst(i3
; RV32IA-LABEL: atomic_store_i32_seq_cst:
; RV32IA: # %bb.0:
; RV32IA-NEXT: fence rw, w
-; RV32IA-NEXT: sw a0, 0(a1)
+; RV32IA-NEXT: sw a1, 0(a0)
; RV32IA-NEXT: ret
store atomic i32 %b, i32* %a seq_cst, align 4
ret void
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