[PATCH] D51284: [X86] When lowering v32i8 MULHS/MULHU, shuffle after the PACKUS rather than before.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: RKSimon, spatel.

We're using a 256-bit PACKUS to do the truncation, but that instruction operates on 128-bit lanes. So previously we shuffled first to rearrange the lanes. But that requires 2 shuffles. Instead we can shuffle after the PACKUS using a single VPERMQ. This matches what our normal LowerTRUNCATE code does when it uses PACKUS.


Repository:
  rL LLVM

https://reviews.llvm.org/D51284

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/vector-idiv-sdiv-256.ll
  test/CodeGen/X86/vector-idiv-sdiv-512.ll
  test/CodeGen/X86/vector-idiv-udiv-256.ll
  test/CodeGen/X86/vector-idiv-udiv-512.ll

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