[PATCH] D51254: [X86] Replace support for vXi32 SMUL_LOHI/UMUL_LOHI with MULHS/MULHU support instead.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: lib/Target/X86/X86ISelLowering.cpp:22899
+
+    int NumElts = VT.getVectorNumElements();
+
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RKSimon wrote:
> Worth pulling out Op0/Op1/NumElts/IsSigned out into common code? We're repeating it in iXi8 lowering as well
I'll do it as a follow up since everything is very slightly different. Op0/Op1 in i32 and A/B in i8. NumElts is int in i32 and unsigned in i8. i8 is checking for !IsSigned really.


Repository:
  rL LLVM

https://reviews.llvm.org/D51254