[llvm] r340682 - [X86] Make requested test changes from D50636
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sat Aug 25 07:16:04 PDT 2018
Author: rksimon
Date: Sat Aug 25 07:16:03 2018
New Revision: 340682
URL: http://llvm.org/viewvc/llvm-project?rev=340682&view=rev
Log:
[X86] Make requested test changes from D50636
The tests were relying on X / X -> 1 and X % X -> 0 combines not happening in the DAG.
Modified:
llvm/trunk/test/CodeGen/X86/2006-11-17-IllegalMove.ll
llvm/trunk/test/CodeGen/X86/combine-srem.ll
llvm/trunk/test/CodeGen/X86/known-bits.ll
Modified: llvm/trunk/test/CodeGen/X86/2006-11-17-IllegalMove.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2006-11-17-IllegalMove.ll?rev=340682&r1=340681&r2=340682&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2006-11-17-IllegalMove.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2006-11-17-IllegalMove.ll Sat Aug 25 07:16:03 2018
@@ -12,7 +12,7 @@ define void @handle_vector_size_attribut
; CHECK-NEXT: movb 0, %al
; CHECK-NEXT: movzbl %al, %eax
; CHECK-NEXT: # kill: def $eax killed $eax def $ax
-; CHECK-NEXT: divb %al
+; CHECK-NEXT: divb 0
; CHECK-NEXT: movzbl %al, %eax
; CHECK-NEXT: cmpq %rax, %rax
; CHECK-NEXT: .LBB0_2: # %bb84
@@ -26,7 +26,7 @@ entry:
bb77: ; preds = %entry, %entry
%tmp99 = udiv i64 0, 0 ; <i64> [#uses=1]
- %tmp = load i8, i8* null ; <i8> [#uses=1]
+ %tmp = load volatile i8, i8* null ; <i8> [#uses=1]
%tmp114 = icmp eq i64 0, 0 ; <i1> [#uses=1]
br label %cond_true115
@@ -34,7 +34,7 @@ bb84: ; preds = %entry
ret void
cond_true115: ; preds = %bb77
- %tmp118 = load i8, i8* null ; <i8> [#uses=1]
+ %tmp118 = load volatile i8, i8* null ; <i8> [#uses=1]
br label %cond_true120
cond_true120: ; preds = %cond_true115
Modified: llvm/trunk/test/CodeGen/X86/combine-srem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-srem.ll?rev=340682&r1=340681&r2=340682&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-srem.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-srem.ll Sat Aug 25 07:16:03 2018
@@ -473,25 +473,33 @@ define i32 @ossfuzz6883() {
; CHECK-LABEL: ossfuzz6883:
; CHECK: # %bb.0:
; CHECK-NEXT: movl (%rax), %ecx
-; CHECK-NEXT: movl %ecx, %eax
-; CHECK-NEXT: cltd
+; CHECK-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
+; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: idivl %ecx
-; CHECK-NEXT: movl %edx, %esi
-; CHECK-NEXT: movl $1, %edi
+; CHECK-NEXT: movl %eax, %esi
+; CHECK-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: divl %ecx
+; CHECK-NEXT: movl %eax, %edi
+; CHECK-NEXT: movl %esi, %eax
; CHECK-NEXT: cltd
; CHECK-NEXT: idivl %edi
+; CHECK-NEXT: movl %edx, %esi
+; CHECK-NEXT: movl %ecx, %eax
+; CHECK-NEXT: cltd
+; CHECK-NEXT: idivl %esi
; CHECK-NEXT: movl %edx, %edi
; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: movl %ecx, %eax
-; CHECK-NEXT: divl %edi
-; CHECK-NEXT: andl %esi, %eax
+; CHECK-NEXT: divl %esi
+; CHECK-NEXT: andl %edi, %eax
; CHECK-NEXT: retq
%B17 = or i32 0, 2147483647
%L6 = load i32, i32* undef
- %B11 = sdiv i32 %L6, %L6
- %B13 = udiv i32 %B17, %B17
+ %B11 = sdiv i32 %B17, %L6
+ %B13 = udiv i32 %B17, %L6
%B14 = srem i32 %B11, %B13
- %B16 = srem i32 %L6, %L6
+ %B16 = srem i32 %L6, %B14
%B10 = udiv i32 %L6, %B14
%B6 = and i32 %B16, %B10
ret i32 %B6
Modified: llvm/trunk/test/CodeGen/X86/known-bits.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/known-bits.ll?rev=340682&r1=340681&r2=340682&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/known-bits.ll (original)
+++ llvm/trunk/test/CodeGen/X86/known-bits.ll Sat Aug 25 07:16:03 2018
@@ -9,34 +9,46 @@ define void @knownbits_zext_in_reg(i8*)
; X32-NEXT: pushl %ebx
; X32-NEXT: pushl %edi
; X32-NEXT: pushl %esi
+; X32-NEXT: subl $16, %esp
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: movzbl (%eax), %eax
-; X32-NEXT: imull $101, %eax, %eax
+; X32-NEXT: movzbl (%eax), %ecx
+; X32-NEXT: imull $101, %ecx, %eax
; X32-NEXT: shrl $14, %eax
+; X32-NEXT: imull $177, %ecx, %ecx
+; X32-NEXT: shrl $14, %ecx
; X32-NEXT: movzbl %al, %eax
-; X32-NEXT: vmovd %eax, %xmm0
-; X32-NEXT: vpshufb {{.*#+}} xmm0 = zero,zero,zero,zero,xmm0[0],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
-; X32-NEXT: vpextrd $1, %xmm0, %ebp
+; X32-NEXT: vpxor %xmm0, %xmm0, %xmm0
+; X32-NEXT: vpinsrd $1, %eax, %xmm0, %xmm1
+; X32-NEXT: vmovdqa {{.*#+}} xmm2 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0]
+; X32-NEXT: vpand %xmm2, %xmm1, %xmm1
+; X32-NEXT: movzbl %cl, %eax
+; X32-NEXT: vpinsrd $1, %eax, %xmm0, %xmm0
+; X32-NEXT: vpand %xmm2, %xmm0, %xmm0
+; X32-NEXT: vpextrd $1, %xmm1, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
+; X32-NEXT: vpextrd $1, %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X32-NEXT: xorl %ecx, %ecx
-; X32-NEXT: vmovd %xmm0, %esi
-; X32-NEXT: vpextrd $2, %xmm0, %edi
-; X32-NEXT: vpextrd $3, %xmm0, %ebx
+; X32-NEXT: vmovd %xmm1, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
+; X32-NEXT: vmovd %xmm0, (%esp) # 4-byte Folded Spill
+; X32-NEXT: vpextrd $2, %xmm1, %edi
+; X32-NEXT: vpextrd $2, %xmm0, %esi
+; X32-NEXT: vpextrd $3, %xmm1, %ebx
+; X32-NEXT: vpextrd $3, %xmm0, %ebp
; X32-NEXT: .p2align 4, 0x90
; X32-NEXT: .LBB0_1: # %CF
; X32-NEXT: # =>This Loop Header: Depth=1
; X32-NEXT: # Child Loop BB0_2 Depth 2
; X32-NEXT: xorl %edx, %edx
-; X32-NEXT: movl %ebp, %eax
-; X32-NEXT: divl %ebp
+; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X32-NEXT: divl {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload
; X32-NEXT: xorl %edx, %edx
-; X32-NEXT: movl %esi, %eax
-; X32-NEXT: divl %esi
+; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X32-NEXT: divl (%esp) # 4-byte Folded Reload
; X32-NEXT: xorl %edx, %edx
; X32-NEXT: movl %edi, %eax
-; X32-NEXT: divl %edi
+; X32-NEXT: divl %esi
; X32-NEXT: xorl %edx, %edx
; X32-NEXT: movl %ebx, %eax
-; X32-NEXT: divl %ebx
+; X32-NEXT: divl %ebp
; X32-NEXT: .p2align 4, 0x90
; X32-NEXT: .LBB0_2: # %CF237
; X32-NEXT: # Parent Loop BB0_1 Depth=1
@@ -47,33 +59,46 @@ define void @knownbits_zext_in_reg(i8*)
;
; X64-LABEL: knownbits_zext_in_reg:
; X64: # %bb.0: # %BB
+; X64-NEXT: pushq %rbp
+; X64-NEXT: pushq %rbx
; X64-NEXT: movzbl (%rdi), %eax
-; X64-NEXT: imull $101, %eax, %eax
+; X64-NEXT: imull $101, %eax, %ecx
+; X64-NEXT: shrl $14, %ecx
+; X64-NEXT: imull $177, %eax, %eax
; X64-NEXT: shrl $14, %eax
+; X64-NEXT: movzbl %cl, %ecx
+; X64-NEXT: vpxor %xmm0, %xmm0, %xmm0
+; X64-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm1
+; X64-NEXT: vmovdqa {{.*#+}} xmm2 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0]
+; X64-NEXT: vpand %xmm2, %xmm1, %xmm1
; X64-NEXT: movzbl %al, %eax
-; X64-NEXT: vmovd %eax, %xmm0
-; X64-NEXT: vpshufb {{.*#+}} xmm0 = zero,zero,zero,zero,xmm0[0],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
-; X64-NEXT: vpextrd $1, %xmm0, %r8d
+; X64-NEXT: vpinsrd $1, %eax, %xmm0, %xmm0
+; X64-NEXT: vpand %xmm2, %xmm0, %xmm0
+; X64-NEXT: vpextrd $1, %xmm1, %r8d
+; X64-NEXT: vpextrd $1, %xmm0, %r9d
; X64-NEXT: xorl %esi, %esi
-; X64-NEXT: vmovd %xmm0, %r9d
-; X64-NEXT: vpextrd $2, %xmm0, %edi
-; X64-NEXT: vpextrd $3, %xmm0, %ecx
+; X64-NEXT: vmovd %xmm1, %r10d
+; X64-NEXT: vmovd %xmm0, %r11d
+; X64-NEXT: vpextrd $2, %xmm1, %edi
+; X64-NEXT: vpextrd $2, %xmm0, %ebx
+; X64-NEXT: vpextrd $3, %xmm1, %ecx
+; X64-NEXT: vpextrd $3, %xmm0, %ebp
; X64-NEXT: .p2align 4, 0x90
; X64-NEXT: .LBB0_1: # %CF
; X64-NEXT: # =>This Loop Header: Depth=1
; X64-NEXT: # Child Loop BB0_2 Depth 2
; X64-NEXT: xorl %edx, %edx
; X64-NEXT: movl %r8d, %eax
-; X64-NEXT: divl %r8d
-; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: movl %r9d, %eax
; X64-NEXT: divl %r9d
; X64-NEXT: xorl %edx, %edx
+; X64-NEXT: movl %r10d, %eax
+; X64-NEXT: divl %r11d
+; X64-NEXT: xorl %edx, %edx
; X64-NEXT: movl %edi, %eax
-; X64-NEXT: divl %edi
+; X64-NEXT: divl %ebx
; X64-NEXT: xorl %edx, %edx
; X64-NEXT: movl %ecx, %eax
-; X64-NEXT: divl %ecx
+; X64-NEXT: divl %ebp
; X64-NEXT: .p2align 4, 0x90
; X64-NEXT: .LBB0_2: # %CF237
; X64-NEXT: # Parent Loop BB0_1 Depth=1
@@ -85,11 +110,13 @@ BB:
%L5 = load i8, i8* %0
%Sl9 = select i1 true, i8 %L5, i8 undef
%B21 = udiv i8 %Sl9, -93
+ %B22 = udiv i8 %Sl9, 93
br label %CF
CF: ; preds = %CF246, %BB
%I40 = insertelement <4 x i8> zeroinitializer, i8 %B21, i32 1
- %B41 = srem <4 x i8> %I40, %I40
+ %I41 = insertelement <4 x i8> zeroinitializer, i8 %B22, i32 1
+ %B41 = srem <4 x i8> %I40, %I41
br label %CF237
CF237: ; preds = %CF237, %CF
More information about the llvm-commits
mailing list