[PATCH] D51231: [X86] Remove Feature64Bit

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: RKSimon, DavidKreitzer, spatel.
Herald added a subscriber: jfb.

The only place that uses this feature is an assert to make sure 64bit is supported when 64-bit mode is being used. But we explicilty add "+64bit" to the feature string in 64-bit mode. So the only way that assert can fail is if the user explicitly wrote -mattr=-64bit. But doing that would trigger the assert and accomplish nothing else. And there's no reason to ever do -mattr=+64bit.

So I think this feature flag is useless.


https://reviews.llvm.org/D51231

Files:
  lib/Target/X86/X86.td
  lib/Target/X86/X86Subtarget.cpp
  lib/Target/X86/X86Subtarget.h
  test/CodeGen/X86/sse_reload_fold.ll
  test/CodeGen/X86/x86-mixed-alignment-dagcombine.ll


Index: test/CodeGen/X86/x86-mixed-alignment-dagcombine.ll
===================================================================
--- test/CodeGen/X86/x86-mixed-alignment-dagcombine.ll
+++ test/CodeGen/X86/x86-mixed-alignment-dagcombine.ll
@@ -1,4 +1,4 @@
-; RUN: llc  -mtriple=x86_64-apple-macosx10.9.0  -mcpu=core2 -mattr=+64bit,+sse2 < %s | FileCheck %s
+; RUN: llc  -mtriple=x86_64-apple-macosx10.9.0  -mcpu=core2 -mattr=+sse2 < %s | FileCheck %s
 
 ; DAGCombine may choose to rewrite 2 loads feeding a select as a select of
 ; addresses feeding a load. This test ensures that when it does that it creates
Index: test/CodeGen/X86/sse_reload_fold.ll
===================================================================
--- test/CodeGen/X86/sse_reload_fold.ll
+++ test/CodeGen/X86/sse_reload_fold.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=x86_64-linux -mattr=+64bit,+sse3 -print-failed-fuse-candidates -regalloc=basic 2>&1 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-linux -mattr=+sse3 -print-failed-fuse-candidates -regalloc=basic 2>&1 | FileCheck %s
 ; CHECK: fail
 ; CHECK-NOT: fail
 
Index: lib/Target/X86/X86Subtarget.h
===================================================================
--- lib/Target/X86/X86Subtarget.h
+++ lib/Target/X86/X86Subtarget.h
@@ -103,9 +103,6 @@
   /// (generally pentium pro+).
   bool HasCMov = false;
 
-  /// True if the processor supports X86-64 instructions.
-  bool HasX86_64 = false;
-
   /// True if the processor supports POPCNT.
   bool HasPOPCNT = false;
 
Index: lib/Target/X86/X86Subtarget.cpp
===================================================================
--- lib/Target/X86/X86Subtarget.cpp
+++ lib/Target/X86/X86Subtarget.cpp
@@ -227,9 +227,9 @@
   std::string FullFS = FS;
   if (In64BitMode) {
     if (!FullFS.empty())
-      FullFS = "+64bit,+sse2," + FullFS;
+      FullFS = "+sse2," + FullFS;
     else
-      FullFS = "+64bit,+sse2";
+      FullFS = "+sse2";
   }
 
   // LAHF/SAHF are always supported in non-64-bit mode.
@@ -263,9 +263,7 @@
 
   LLVM_DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel
                     << ", 3DNowLevel " << X863DNowLevel << ", 64bit "
-                    << HasX86_64 << "\n");
-  assert((!In64BitMode || HasX86_64) &&
-         "64-bit code requested on a subtarget that doesn't support it!");
+                    << In64BitMode << "\n");
 
   // Stack alignment is 16 bytes on Darwin, Linux, kFreeBSD and Solaris (both
   // 32 and 64 bit) and for all 64-bit targets.
Index: lib/Target/X86/X86.td
===================================================================
--- lib/Target/X86/X86.td
+++ lib/Target/X86/X86.td
@@ -86,14 +86,8 @@
 def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
                                       "Enable 3DNow! Athlon instructions",
                                       [Feature3DNow]>;
-// All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
-// feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
-// without disabling 64-bit mode.
-def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
-                                      "Support 64-bit instructions">;
 def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
-                                      "64-bit with cmpxchg16b",
-                                      [Feature64Bit]>;
+                                      "64-bit with cmpxchg16b">;
 def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
                                        "SHLD instruction is slow">;
 def FeatureSlowPMULLD : SubtargetFeature<"slow-pmulld", "IsPMULLDSlow", "true",
@@ -920,7 +914,7 @@
 
 foreach P = ["k8", "opteron", "athlon64", "athlon-fx"] in {
   def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
-                 FeatureFXSR, FeatureNOPL, Feature64Bit, FeatureSlowSHLD,
+                 FeatureFXSR, FeatureNOPL, FeatureSlowSHLD,
                  FeatureCMOV]>;
 }
 
@@ -1160,7 +1154,6 @@
   FeatureSSE2,
   FeatureFXSR,
   FeatureNOPL,
-  Feature64Bit,
   FeatureSlow3OpsLEA,
   FeatureSlowIncDec,
   FeatureMacroFusion


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