[PATCH] D50578: [DAGCombiner][Mips] Don't combine bitcast+store after LegalOperations when the store is volatile, if the resulting store isn't Legal

[Phabricator via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL340626: [DAGCombiner][Mips] Don't combine bitcast+store after LegalOperations when the… (authored by ctopper, committed by ).
Herald added a subscriber: jrtc27.

Changed prior to commit:
  https://reviews.llvm.org/D50578?vs=160170&id=162419#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D50578

Files:
  llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/trunk/test/CodeGen/Mips/cconv/arguments-hard-float-varargs.ll
  llvm/trunk/test/CodeGen/Mips/cconv/arguments-hard-float.ll


Index: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -14684,7 +14684,7 @@
       ST->isUnindexed()) {
     EVT SVT = Value.getOperand(0).getValueType();
     if (((!LegalOperations && !ST->isVolatile()) ||
-         TLI.isOperationLegalOrCustom(ISD::STORE, SVT)) &&
+         TLI.isOperationLegal(ISD::STORE, SVT)) &&
         TLI.isStoreBitCastBeneficial(Value.getValueType(), SVT)) {
       unsigned OrigAlign = ST->getAlignment();
       bool Fast = false;
Index: llvm/trunk/test/CodeGen/Mips/cconv/arguments-hard-float-varargs.ll
===================================================================
--- llvm/trunk/test/CodeGen/Mips/cconv/arguments-hard-float-varargs.ll
+++ llvm/trunk/test/CodeGen/Mips/cconv/arguments-hard-float-varargs.ll
@@ -111,7 +111,8 @@
 
 ; The first four arguments are the same in O32/N32/N64.
 ; The non-variable portion should be unaffected.
-; O32-DAG:           sw $4, 4([[R2]])
+; O32-DAG:           mtc1 $4, $f0
+; O32-DAG:           swc1 $f0, 4([[R2]])
 ; NEW-DAG:           swc1 $f12, 4([[R2]])
 
 ; The varargs portion is dumped to stack
Index: llvm/trunk/test/CodeGen/Mips/cconv/arguments-hard-float.ll
===================================================================
--- llvm/trunk/test/CodeGen/Mips/cconv/arguments-hard-float.ll
+++ llvm/trunk/test/CodeGen/Mips/cconv/arguments-hard-float.ll
@@ -125,9 +125,11 @@
 ; I've yet to find a reference in the documentation about this but GCC uses up
 ; the remaining two argument slots in the GPR's first. We'll do the same for
 ; compatibility.
-; O32-DAG:           sw $6, 12([[R1]])
+; O32-DAG:           mtc1 $6, $f0
+; O32-DAG:           swc1 $f0, 12([[R1]])
 ; NEW-DAG:           swc1 $f14, 12([[R1]])
-; O32-DAG:           sw $7, 16([[R1]])
+; O32-DAG:           mtc1 $7, $f0
+; O32-DAG:           swc1 $f0, 16([[R1]])
 ; NEW-DAG:           swc1 $f15, 16([[R1]])
 
 ; O32 is definitely out of registers now and switches to the stack.
@@ -207,5 +209,6 @@
 ; MD00305 and GCC disagree on this one. MD00305 says that floats are treated
 ; as 8-byte aligned and occupy two slots on O32. GCC is treating them as 4-byte
 ; aligned and occupying one slot. We'll use GCC's definition.
-; O32-DAG:           sw $5, 4([[R2]])
+; O32-DAG:           mtc1 $5, $f0
+; O32-DAG:           swc1 $f0, 4([[R2]])
 ; NEW-DAG:           swc1 $f13, 4([[R2]])


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D50578.162419.patch
Type: text/x-patch
Size: 2518 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20180824/b2659732/attachment.bin>