[PATCH] D50614: DAG: Allow matching fminnum/fmaxnum from vselect

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon accepted this revision.
RKSimon added a comment.

LGTM - not sure if its any better to split fmin_fmax_legacy.f16.ll into fmin_legacy.f16.ll and fmax_legacy.f16.ll - I find it sometimes useful to be able to diff these types of related test files against one another?



================
Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:7295
     //
-
-    // FIXME: This should be checking for no signed zeros on individual
-    // operands, as well as no nans.
-    const TargetOptions &Options = DAG.getTarget().Options;
-    if (Options.NoSignedZerosFPMath && VT.isFloatingPoint() && N0.hasOneUse() &&
-        DAG.isKnownNeverNaN(N1) && DAG.isKnownNeverNaN(N2)) {
+    if (N0.hasOneUse() && isLegalToCombineMinNumMaxNum(DAG, N1, N2)) {
       ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
----------------
This bit can be comitted first as a NFC helper change?


https://reviews.llvm.org/D50614