[PATCH] D50982: [AMDGPU] Legalize VGPR Rsrc operands for MUBUF instructions

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: test/CodeGen/AMDGPU/mubuf-legalize-operands.ll:12
+; CHECK-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v3
+; CHECK-NOT: DAG-DIVIDER
+; CHECK-DAG: v_cmp_eq_u64_e32 vcc, s{{\[}}[[SRSRC0]]:[[SRSRC1]]{{\]}}, v[0:1]
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scott.linder wrote:
> arsenm wrote:
> > What's this?
> This is me trying to be sure the uses occurs after the defs, even though the order within each doesn't matter. My understanding is that without the divider the cmp's could appear before the readfirstlanes and because they are adjacent -DAG it would still match. The chances of it seem low, and maybe there is a better way than a dummy CHECK-NOT to prevent it?
I'm not sure that's how CHECK-NOT works, although there were some recent changes to try to clarify the behavior of CHECK-DAG I haven't looked into


https://reviews.llvm.org/D50982