[PATCH] D51203: AMDGPU: Handle 32-bit address wraparounds for SMRD opcodes

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: test/CodeGen/AMDGPU/constant-address-space-32bit.ll:289
+define amdgpu_vs float @load_addr_no_fold(i32 addrspace(6)* inreg %p0) #0 {
+  %gep1 = getelementptr i32, i32 addrspace(6)* %p0, i64 65537
+  %r1 = load i32, i32 addrspace(6)* %gep1
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The constant should canonically be i32


Repository:
  rL LLVM

https://reviews.llvm.org/D51203