[llvm] r340318 - [RegisterCoalscer] Manually remove leftover segments when commuting def

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Tue Aug 21 12:01:26 2018
New Revision: 340318

URL: http://llvm.org/viewvc/llvm-project?rev=340318&view=rev
Log:
[RegisterCoalscer] Manually remove leftover segments when commuting def

In removeCopyByCommutingDef, segments from the source live range are
copied into (and merged with) the segments of the target live range.
This is performed for all subranges of the source interval. It can
happen that there will be subranges of the target interval that had
no corresponding subranges in the source interval, and in such cases
these subrages will not be updated. Since the copy being coalesced
is about to be removed, these ranges need to be updated by removing
the segments that are started by the copy.

Added:
    llvm/trunk/test/CodeGen/SystemZ/subregliveness-07.mir
Modified:
    llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp

Modified: llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp?rev=340318&r1=340317&r2=340318&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp Tue Aug 21 12:01:26 2018
@@ -902,9 +902,11 @@ RegisterCoalescer::removeCopyByCommuting
       IntB.createSubRangeFrom(Allocator, Mask, IntB);
     }
     SlotIndex AIdx = CopyIdx.getRegSlot(true);
+    LaneBitmask MaskA;
     for (LiveInterval::SubRange &SA : IntA.subranges()) {
       VNInfo *ASubValNo = SA.getVNInfoAt(AIdx);
       assert(ASubValNo != nullptr);
+      MaskA |= SA.LaneMask;
 
       IntB.refineSubRanges(Allocator, SA.LaneMask,
           [&Allocator,&SA,CopyIdx,ASubValNo,&ShrinkB]
@@ -919,6 +921,16 @@ RegisterCoalescer::removeCopyByCommuting
           BSubValNo->def = ASubValNo->def;
       });
     }
+    // Go over all subranges of IntB that have not been covered by IntA,
+    // and delete the segments starting at CopyIdx. This can happen if
+    // IntA has undef lanes that are defined in IntB.
+    for (LiveInterval::SubRange &SB : IntB.subranges()) {
+      if ((SB.LaneMask & MaskA).any())
+        continue;
+      if (LiveRange::Segment *S = SB.getSegmentContaining(CopyIdx))
+        if (S->start.getBaseIndex() == CopyIdx.getBaseIndex())
+          SB.removeSegment(*S, true);
+    }
   }
 
   BValNo->def = AValNo->def;

Added: llvm/trunk/test/CodeGen/SystemZ/subregliveness-07.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/subregliveness-07.mir?rev=340318&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/subregliveness-07.mir (added)
+++ llvm/trunk/test/CodeGen/SystemZ/subregliveness-07.mir Tue Aug 21 12:01:26 2018
@@ -0,0 +1,78 @@
+# RUN: llc -mtriple=s390x-ibm-linux -systemz-subreg-liveness -verify-machineinstrs -start-before=simple-register-coalescing -o - %s | FileCheck %s
+
+# Check for successful compilation.
+# CHECK: lhi %r0, 0
+
+--- |
+  target datalayout = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-v128:64-a:8:16-n32:64"
+  target triple = "s390x-ibm-linux"
+
+  @g_105 = external dso_local global i8, align 2
+  @g_149 = external dso_local unnamed_addr global i8, align 2
+
+  define void @main() #0 {
+    ret void
+  }
+  attributes #0 = { nounwind "target-cpu"="z13" "target-features"="+transactional-execution,+vector" }
+...
+
+---
+name:            main
+alignment:       4
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    %8:grx32bit = LHIMux 0
+    %9:gr64bit = LGHI 0
+    %17:addr64bit = LARL @g_105
+    %19:grx32bit = IMPLICIT_DEF
+    %20:gr32bit = COPY %8
+    %21:gr32bit = COPY %8
+
+  bb.1:
+    successors: %bb.3(0x7fffffff), %bb.2(0x00000001)
+
+    %2:gr32bit = COPY killed %21
+    %1:gr32bit = COPY killed %20
+    %0:grx32bit = COPY killed %19
+    TMLMux killed %0, 255, implicit-def $cc
+    %3:gr64bit = COPY %9
+    %3:gr64bit = LOCGHI %3, 1, 15, 7, implicit $cc
+    BRC 15, 8, %bb.3, implicit killed $cc
+    J %bb.2
+
+  bb.2:
+    successors:
+
+  bb.3:
+    %10:gr32bit = COPY killed %2
+    %10:gr32bit = OR %10, killed %1, implicit-def dead $cc
+    undef %11.subreg_l32:gr64bit = COPY killed %10
+    %13:gr64bit = COPY killed %11
+    %13:gr64bit = ROSBG %13, killed %3, 32, 63, 0, implicit-def dead $cc
+    CHIMux %8, 0, implicit-def $cc
+    BRC 14, 6, %bb.5, implicit killed $cc
+    J %bb.4
+
+  bb.4:
+
+  bb.5:
+    successors: %bb.7(0x00000001), %bb.6(0x7fffffff)
+
+    %4:grx32bit = COPY killed %13.subreg_l32
+    CHIMux undef %16:grx32bit, 10, implicit-def $cc
+    BRC 14, 8, %bb.7, implicit killed $cc
+    J %bb.6
+
+  bb.6:
+    %6:grx32bit = LBMux %17, 0, $noreg :: (dereferenceable load 1 from @g_105, align 2)
+    %19:grx32bit = COPY killed %6
+    %20:gr32bit = COPY killed %4
+    %21:gr32bit = IMPLICIT_DEF
+    J %bb.1
+
+  bb.7:
+    %18:addr64bit = LARL @g_149
+    STCMux killed %4, killed %18, 0, $noreg :: (store 1 into @g_149, align 2)
+
+...