[PATCH] D50981: [X86] Prevent lowerVectorShuffleByMerging128BitLanes from creating cycles
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Mon Aug 20 14:09:45 PDT 2018
This revision was automatically updated to reflect the committed changes.
Closed by commit rL340214: [X86] Prevent lowerVectorShuffleByMerging128BitLanes from creating cycles (authored by ctopper, committed by ).
Changed prior to commit:
https://reviews.llvm.org/D50981?vs=161514&id=161562#toc
Repository:
rL LLVM
https://reviews.llvm.org/D50981
Files:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/test/CodeGen/X86/pr38639.ll
Index: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
@@ -13470,6 +13470,12 @@
}
}
SDValue NewV1 = DAG.getVectorShuffle(VT, DL, V1, V2, NewMask);
+ // Ensure we didn't get back the shuffle we started with.
+ // FIXME: This is a hack to make up for some splat handling code in
+ // getVectorShuffle.
+ if (isa<ShuffleVectorSDNode>(NewV1) &&
+ cast<ShuffleVectorSDNode>(NewV1)->getMask() == Mask)
+ return SDValue();
for (int Lane = 0; Lane != NumLanes; ++Lane) {
int Src = LaneSrcs[Lane][1];
@@ -13481,6 +13487,12 @@
}
}
SDValue NewV2 = DAG.getVectorShuffle(VT, DL, V1, V2, NewMask);
+ // Ensure we didn't get back the shuffle we started with.
+ // FIXME: This is a hack to make up for some splat handling code in
+ // getVectorShuffle.
+ if (isa<ShuffleVectorSDNode>(NewV2) &&
+ cast<ShuffleVectorSDNode>(NewV2)->getMask() == Mask)
+ return SDValue();
for (int i = 0; i != Size; ++i) {
NewMask[i] = RepeatMask[i % LaneSize];
Index: llvm/trunk/test/CodeGen/X86/pr38639.ll
===================================================================
--- llvm/trunk/test/CodeGen/X86/pr38639.ll
+++ llvm/trunk/test/CodeGen/X86/pr38639.ll
@@ -0,0 +1,18 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=btver2 | FileCheck %s
+
+define <8 x double> @test(<4 x double> %a, <4 x double> %b) {
+; CHECK-LABEL: test:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmovaps {{.*#+}} ymm2 = <u,0.82071743224100002,0.82071743224100002,0.82071743224100002>
+; CHECK-NEXT: vextractf128 $1, %ymm2, %xmm4
+; CHECK-NEXT: vblendps {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm2[4,5,6,7]
+; CHECK-NEXT: vblendps {{.*#+}} ymm3 = ymm0[0,1],ymm2[2,3],ymm0[4,5,6,7]
+; CHECK-NEXT: vblendps {{.*#+}} xmm2 = xmm4[0,1],xmm2[2,3]
+; CHECK-NEXT: vunpckhpd {{.*#+}} ymm1 = ymm3[1],ymm1[1],ymm3[3],ymm1[3]
+; CHECK-NEXT: vblendps {{.*#+}} ymm0 = ymm2[0,1,2,3],ymm0[4,5,6,7]
+; CHECK-NEXT: retq
+ %1 = shufflevector <4 x double> %a, <4 x double> <double undef, double 0x3FEA435134576E1C, double 0x3FEA435134576E1C, double 0x3FEA435134576E1C>, <8 x i32> <i32 6, i32 5, i32 2, i32 3, i32 5, i32 1, i32 3, i32 7>
+ ret <8 x double> %1
+}
+
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