[PATCH] D46423: [WIP, RISCV] Support .option relax and .option norelax

[Shiva Chen via Phabricator via llvm-commits]

shiva0217 added a comment.

Apology. I thought the assembler will parse all the instructions and then do the encoding which is incorrect. It will parse and encode one instruction at a time. So we don't need using MCinst's Flag to record the instruction state and NoRelaxLocStart shouldn't need.
We could define `FeatureNoRelaxREL` feature to indicate the suppression of `R_RISCV_RELAX` relocation type instead of clear `FeatureRelax` bit.
Because once the `.option relax` occur in the file,  shouldForceRelocation, and requiresDiffExpressionRelocations should return true to make sure the local branches and label differences will leave the relocation types.
With the relocation types, the linker relaxation could do the right adjustment when the code size changed. 
I think it's quite familiar with the approach @simoncook  mention in https://reviews.llvm.org/D45181#1086541.
Is it a feasible way to implement? or we may still break something in certain cases?

  if (Option == "relax") {
    getTargetStreamer().emitDirectiveOptionRelax();
  
    Parser.Lex();
    if (Parser.getTok().isNot(AsmToken::EndOfStatement))
      return Error(Parser.getTok().getLoc(),
                   "unexpected token, expected end of statement");
  
    setFeatureBits(RISCV::FeatureRelax, "relax");
   + clearFeatureBits(RISCV::FeatureNoRelaxREL, "norelaxrel");
  
    // Update AsmBackend with new STI
    getTargetStreamer().getStreamer().getAssemblerPtr()->getBackend()
        .setSTI(getSTI());
    return false;
  }
  
  if (Option == "norelax") {
    getTargetStreamer().emitDirectiveOptionNoRelax();
  
    Parser.Lex();
    if (Parser.getTok().isNot(AsmToken::EndOfStatement))
      return Error(Parser.getTok().getLoc(),
                   "unexpected token, expected end of statement");
  
    + setFeatureBits(RISCV::FeatureNoRelaxREL, "norelaxrel");
    // Update AsmBackend with new STI
    getTargetStreamer().getStreamer().getAssemblerPtr()->getBackend()
        .setSTI(getSTI());
    return false;
  }
  
   +++ b/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
  @@ -258,7 +258,7 @@ unsigned RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
         MCFixup::create(0, Expr, MCFixupKind(FixupKind), MI.getLoc()));
     ++MCNumFixups;
  
   -  if (EnableRelax) {
   +  bool NoRelaxREL = STI.getFeatureBits()[RISCV::FeatureNoRelaxREL];
   +  if (EnableRelax && (!NoRelaxREL)) {
         // Emit R_RISCV_RELAX relocation type.


Repository:
  rL LLVM

https://reviews.llvm.org/D46423