[PATCH] D47882: [RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32A

[Alex Bradbury via Phabricator via llvm-commits]

asb added inline comments.
Herald added a subscriber: jocewei.


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Comment at: lib/CodeGen/AtomicExpandPass.cpp:888
+                        PMV.ShiftAmt, "ValOperand_Shifted");
+  Value *OldResult = TLI->emitMaskedAtomicRMWIntrinsic(
+      Builder, AI, PMV.AlignedAddr, ValOperand_Shifted, PMV.Mask,
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jyknight wrote:
> For the OR, XOR, and AND operations, there's no need to implement or use a masked intrinsic at all -- the normal 32bit atomic will do the job fine given ValOperand_Shifted as the argument.
> 
> For the masked AND, you do need to pass "ValOperand_Shifted | PMV.Inv_Mask" instead, of course.
> 
> (I note that I neglected to implement that optimization for AND in the cmpxchg expansion in expandPartwordAtomicRMW.)
> 
Yes I recognise this, and D48129 implements the three optimisations you suggest for RISC-V. I've now reworked that patch so it is target-independent and the same i8/i16 -> i32 transformation logic is used regardless of the AtomicExpansionKind. Let me know what you think,

It probably makes sense to rebase this patch so it is dependent on D48129.


https://reviews.llvm.org/D47882