[PATCH] D50633: [AMDGPU] Add new Mode Register pass

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: lib/Target/AMDGPU/SIModeRegister.cpp:160-180
+// Determine the Mode register setting required for this instruction.
+// Instructions which don't use the Mode register return a null Status.
+// Note this currently only deals with instructions that use the floating point
+// double precision setting.
+Status SIModeRegister::getInstructionMode(MachineInstr &MI,
+                                          const SIInstrInfo *TII) {
+  if (TII->usesFPDPRounding(MI)) {
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timcorringham wrote:
> arsenm wrote:
> > I'm not really comfortable inserting something semantically required at this point. Can you do this when the instructions are selected instead?
> The problem with doing it during instruction selection is that we end up with many more mode register writes than are strictly required. As the mode register is not modelled as a register there isn't any way to track the values without a pass to do it, I suppose it is similar to adding nops or waitcnts, which are also done by specific passes.
This is a semantic property and I think it really belongs in instruction selection. What is the problem with optimizing those out here? What actually changes?


Repository:
  rL LLVM

https://reviews.llvm.org/D50633