[llvm] r340129 - [X86] Simplify the PADDUS legality check in combineSelect to match PSUBUS. NFC

[Craig Topper via llvm-commits]

Author: ctopper
Date: Sat Aug 18 11:51:04 2018
New Revision: 340129

URL: http://llvm.org/viewvc/llvm-project?rev=340129&view=rev
Log:
[X86] Simplify the PADDUS legality check in combineSelect to match PSUBUS. NFC

While there remove some trailing whitespace.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=340129&r1=340128&r2=340129&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sat Aug 18 11:51:04 2018
@@ -33102,9 +33102,10 @@ static SDValue combineSelect(SDNode *N,
 
   // Match VSELECTs into add with unsigned saturation.
   if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
-      ((Subtarget.hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
-       (Subtarget.hasAVX() && (VT == MVT::v32i8 || VT == MVT::v16i16)) ||
-       (Subtarget.useBWIRegs() && (VT == MVT::v64i8 || VT == MVT::v32i16)))) {
+      // paddus is available in SSE2 for i8 and i16 vectors.
+      Subtarget.hasSSE2() &&
+      (VT.getVectorElementType() == MVT::i8 ||
+       VT.getVectorElementType() == MVT::i16)) {
     ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
 
     SDValue CondLHS = Cond->getOperand(0);
@@ -33136,7 +33137,7 @@ static SDValue combineSelect(SDNode *N,
                              ArrayRef<SDValue> Ops) {
         return DAG.getNode(X86ISD::ADDUS, DL, Ops[0].getValueType(), Ops);
       };
-      
+
       // x <= x+y ? x+y : ~0 --> addus x, y
       if ((CC == ISD::SETULE) &&
           Other.getOpcode() == ISD::ADD && Other == CondRHS)