[PATCH] D46179: [X86] Lowering addus/subus intrinsics to native IR (LLVM part)
Simon Pilgrim via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 17 04:25:19 PDT 2018
RKSimon added a comment.
In https://reviews.llvm.org/D46179#1203852, @jgorbe wrote:
> I think this change is breaking one of our builds. The attached reduced test case fails with the current trunk revision if built with "clang -x c -O2 -mavx -c crash.ii".
define void @d() {
entry:
%wide.load = load <4 x i16>, <4 x i16>* undef, align 2
%0 = sext <4 x i16> %wide.load to <4 x i32>
%1 = sub nsw <4 x i32> zeroinitializer, %0
%2 = icmp sgt <4 x i32> %1, <i32 -32768, i32 -32768, i32 -32768, i32 -32768>
%3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768>
%4 = icmp slt <4 x i32> %3, <i32 32767, i32 32767, i32 32767, i32 32767>
%5 = select <4 x i1> %4, <4 x i32> %3, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>
%6 = trunc <4 x i32> %5 to <4 x i16>
store <4 x i16> %6, <4 x i16>* undef, align 2
unreachable
}
Repository:
rL LLVM
https://reviews.llvm.org/D46179
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