[llvm] r339821 - AMDGPU: Fold fneg into fmed3
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 15 14:46:27 PDT 2018
Author: arsenm
Date: Wed Aug 15 14:46:27 2018
New Revision: 339821
URL: http://llvm.org/viewvc/llvm-project?rev=339821&view=rev
Log:
AMDGPU: Fold fneg into fmed3
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.fmed3.ll
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp?rev=339821&r1=339820&r2=339821&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp Wed Aug 15 14:46:27 2018
@@ -562,6 +562,7 @@ static bool fnegFoldsIntoOp(unsigned Opc
case AMDGPUISD::FMUL_LEGACY:
case AMDGPUISD::FMIN_LEGACY:
case AMDGPUISD::FMAX_LEGACY:
+ case AMDGPUISD::FMED3:
return true;
default:
return false;
@@ -3607,6 +3608,16 @@ SDValue AMDGPUTargetLowering::performFNe
if (!N0.hasOneUse())
DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
return Res;
+ }
+ case AMDGPUISD::FMED3: {
+ SDValue Ops[3];
+ for (unsigned I = 0; I < 3; ++I)
+ Ops[I] = DAG.getNode(ISD::FNEG, SL, VT, N0->getOperand(I), N0->getFlags());
+
+ SDValue Res = DAG.getNode(AMDGPUISD::FMED3, SL, VT, Ops, N0->getFlags());
+ if (!N0.hasOneUse())
+ DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
+ return Res;
}
case ISD::FP_EXTEND:
case ISD::FTRUNC:
Modified: llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.fmed3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.fmed3.ll?rev=339821&r1=339820&r2=339821&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.fmed3.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.fmed3.ll Wed Aug 15 14:46:27 2018
@@ -4,8 +4,8 @@
; GCN-LABEL: {{^}}test_fmed3:
; GCN: v_med3_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @test_fmed3(float addrspace(1)* %out, float %src0, float %src1, float %src2) #1 {
- %mad = call float @llvm.amdgcn.fmed3.f32(float %src0, float %src1, float %src2)
- store float %mad, float addrspace(1)* %out
+ %med3 = call float @llvm.amdgcn.fmed3.f32(float %src0, float %src1, float %src2)
+ store float %med3, float addrspace(1)* %out
ret void
}
@@ -16,8 +16,86 @@ define amdgpu_kernel void @test_fmed3_sr
%src1.fabs = call float @llvm.fabs.f32(float %src1)
%src2.fabs = call float @llvm.fabs.f32(float %src2)
%src2.fneg.fabs = fsub float -0.0, %src2.fabs
- %mad = call float @llvm.amdgcn.fmed3.f32(float %src0.fneg, float %src1.fabs, float %src2.fneg.fabs)
- store float %mad, float addrspace(1)* %out
+ %med3 = call float @llvm.amdgcn.fmed3.f32(float %src0.fneg, float %src1.fabs, float %src2.fneg.fabs)
+ store float %med3, float addrspace(1)* %out
+ ret void
+}
+
+; GCN-LABEL: {{^}}test_fneg_fmed3:
+; GCN: v_med3_f32 v{{[0-9]+}}, -s{{[0-9]+}}, -v{{[0-9]+}}, -v{{[0-9]+}}
+define amdgpu_kernel void @test_fneg_fmed3(float addrspace(1)* %out, float %src0, float %src1, float %src2) #1 {
+ %med3 = call float @llvm.amdgcn.fmed3.f32(float %src0, float %src1, float %src2)
+ %neg.med3 = fsub float -0.0, %med3
+ store float %neg.med3, float addrspace(1)* %out
+ ret void
+}
+
+; GCN-LABEL: {{^}}test_fneg_fmed3_multi_use:
+; GCN: v_med3_f32 [[MED3:v[0-9]+]], -s{{[0-9]+}}, -v{{[0-9]+}}, -v{{[0-9]+}}
+; GCN: v_mul_f32_e32 v{{[0-9]+}}, -4.0, [[MED3]]
+define amdgpu_kernel void @test_fneg_fmed3_multi_use(float addrspace(1)* %out, float %src0, float %src1, float %src2) #1 {
+ %med3 = call float @llvm.amdgcn.fmed3.f32(float %src0, float %src1, float %src2)
+ %neg.med3 = fsub float -0.0, %med3
+ %med3.user = fmul float %med3, 4.0
+ store volatile float %med3.user, float addrspace(1)* %out
+ store volatile float %neg.med3, float addrspace(1)* %out
+ ret void
+}
+
+; GCN-LABEL: {{^}}test_fabs_fmed3:
+; GCN: v_med3_f32 [[MED3:v[0-9]+]], s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+; GCN: v_and_b32_e32 v{{[0-9]+}}, 0x7fffffff, [[MED3]]
+define amdgpu_kernel void @test_fabs_fmed3(float addrspace(1)* %out, float %src0, float %src1, float %src2) #1 {
+ %med3 = call float @llvm.amdgcn.fmed3.f32(float %src0, float %src1, float %src2)
+ %fabs.med3 = call float @llvm.fabs.f32(float %med3)
+ store float %fabs.med3, float addrspace(1)* %out
+ ret void
+}
+
+; GCN-LABEL: {{^}}test_fneg_fmed3_rr_0:
+; GCN: v_bfrev_b32_e32 [[NEG0:v[0-9]+]], 1
+; GCN: v_med3_f32 v{{[0-9]+}}, -s{{[0-9]+}}, -v{{[0-9]+}}, [[NEG0]]
+define amdgpu_kernel void @test_fneg_fmed3_rr_0(float addrspace(1)* %out, float %src0, float %src1) #1 {
+ %med3 = call float @llvm.amdgcn.fmed3.f32(float %src0, float %src1, float 0.0)
+ %neg.med3 = fsub float -0.0, %med3
+ store float %neg.med3, float addrspace(1)* %out
+ ret void
+}
+
+; FIXME: Worse off from folding this
+; GCN-LABEL: {{^}}test_fneg_fmed3_rr_0_foldable_user:
+; GCN: v_bfrev_b32_e32 [[NEG0:v[0-9]+]], 1
+; GCN: v_med3_f32 [[MED3:v[0-9]+]], -s{{[0-9]+}}, -v{{[0-9]+}}, [[NEG0]]
+; GCN: v_mul_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[MED3]]
+define amdgpu_kernel void @test_fneg_fmed3_rr_0_foldable_user(float addrspace(1)* %out, float %src0, float %src1, float %mul.arg) #1 {
+ %med3 = call float @llvm.amdgcn.fmed3.f32(float %src0, float %src1, float 0.0)
+ %neg.med3 = fsub float -0.0, %med3
+ %mul = fmul float %neg.med3, %mul.arg
+ store float %mul, float addrspace(1)* %out
+ ret void
+}
+
+; GCN-LABEL: {{^}}test_fneg_fmed3_r_inv2pi_0:
+; GCN-DAG: v_bfrev_b32_e32 [[NEG0:v[0-9]+]], 1
+; GCN-DAG: v_mov_b32_e32 [[NEG_INV:v[0-9]+]], 0xbe22f983
+; GCN: v_med3_f32 v{{[0-9]+}}, -s{{[0-9]+}}, [[NEG_INV]], [[NEG0]]
+define amdgpu_kernel void @test_fneg_fmed3_r_inv2pi_0(float addrspace(1)* %out, float %src0) #1 {
+ %med3 = call float @llvm.amdgcn.fmed3.f32(float %src0, float 0x3FC45F3060000000, float 0.0)
+ %neg.med3 = fsub float -0.0, %med3
+ store float %neg.med3, float addrspace(1)* %out
+ ret void
+}
+
+; GCN-LABEL: {{^}}test_fneg_fmed3_r_inv2pi_0_foldable_user:
+; GCN-DAG: v_bfrev_b32_e32 [[NEG0:v[0-9]+]], 1
+; GCN-DAG: v_mov_b32_e32 [[NEG_INV:v[0-9]+]], 0xbe22f983
+; GCN: v_med3_f32 [[MED3:v[0-9]+]], -s{{[0-9]+}}, [[NEG_INV]], [[NEG0]]
+; GCN: v_mul_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[MED3]]
+define amdgpu_kernel void @test_fneg_fmed3_r_inv2pi_0_foldable_user(float addrspace(1)* %out, float %src0, float %mul.arg) #1 {
+ %med3 = call float @llvm.amdgcn.fmed3.f32(float %src0, float 0x3FC45F3060000000, float 0.0)
+ %neg.med3 = fsub float -0.0, %med3
+ %mul = fmul float %neg.med3, %mul.arg
+ store float %mul, float addrspace(1)* %out
ret void
}
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