[PATCH] D50432: [DAGCombiner] Reduce load widths of shifted masks

[Diogo N. Sampaio via Phabricator via llvm-commits]

dnsampaio added inline comments.


================
Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:9094
     ExtType = ISD::ZEXTLOAD;
     ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
   }
----------------
dnsampaio wrote:
> ActiveBits can be zero, this might throw an error no?
> `and (load i32, 0x000FF000)`
> This is a shifted mask. You could use APInt.countPopulation as to get the number of 1s.
Ignore. u do lsrh.


https://reviews.llvm.org/D50432